Organização de Computadores Fabiano Hessel hessel@inf.pucrs.br hessel

Organização de Computadores

Fabiano Hesselhessel@inf.pucrs.br

http://www.inf.pucrs.br/~hessel

© 2000 Morgan Kaufman

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Bibliografia

Livro texto Patterson, D. A. & Hennessy, J. L.

Organização e projeto de computadores: a interface hardware/software

Livros referenciados e outras referências Disponíveis na página da disciplina

Slides e documentos disponíveis na página

© 2000 Morgan Kaufman

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Conteúdo

Revisão de conceitos básicosProcessador Cleópatra

Características gerais Linguagem assembly Bloco de dados Bloco de controle

VHDL

© 2000 Morgan Kaufman

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Avaliação

2 provas e 1 trabalho práticoFórmula G1

G1= ( P1 + P2 + T ) / 3P1 - 24/ABRILP2 - 01/JULHOP4 - 03/JULHOG2 - 08/JULHO

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Trabalho

Implementar o processador R11, utilizando a linguagem VHDL

Especificação do trabalho prevista para Maio

Apresentação dos trabalhos 24/JULHO 26/JULHO

© 2000 Morgan Kaufman

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Aviso

Semana Acadêmica Durante a semana acadêmica não

haverá aula, estando os alunos e o professor dispensados para acompanhar o evento.

Período: 09 a 13 de Junho

© 2000 Morgan Kaufman

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Embedding a computer

CPU

mem

input

output analog

analog

embeddedcomputer

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Instruction sets

Computer architecture taxonomy.Assembly language.

© 2000 Morgan Kaufman

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von Neumann architecture

Memory holds data, instructions.Central processing unit (CPU) fetches

instructions from memory. Separate CPU and memory

distinguishes programmable computer.CPU registers help out: program

counter (PC), instruction register (IR), general-purpose registers, etc.

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CPU + memory

memoryCPU

PC

address

data

IRADD r5,r1,r3200

200

ADD r5,r1,r3

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Harvard architecture

CPU

PCdata memory

program memory

address

data

address

data

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von Neumann vs. Harvard

Harvard can’t use self-modifying code.

Harvard allows two simultaneous memory fetches.

Most DSPs use Harvard architecture for streaming data: greater memory bandwidth; more predictable bandwidth.

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RISC vs. CISC

Complex instruction set computer (CISC): many addressing modes; many operations.

Reduced instruction set computer (RISC): load/store; pipelinable instructions.

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Instruction set characteristics

Fixed vs. variable length.Addressing modes.Number of operands.Types of operands.

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Programming model

Programming model: registers visible to the programmer.

Some registers are not visible (IR).

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Multiple implementations

Successful architectures have several implementations: varying clock speeds; different bus widths; different cache sizes; etc.

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Assembly language

One-to-one with instructions (more or less).

Basic features: One instruction per line. Labels provide names for addresses

(usually in first column). Instructions often start in later columns. Columns run to end of line.

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ARM assembly language example

label1 ADR r4,cLDR r0,[r4] ; a commentADR r4,dLDR r1,[r4]SUB r0,r0,r1 ; comment

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Pseudo-ops

Some assembler directives don’t correspond directly to instructions: Define current address. Reserve storage. Constants.

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Endianness

Relationship between bit and byte/word ordering defines endianness:

byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3

bit 31 bit 0 bit 0 bit 31

little-endian big-endian

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Example: C assignments (ARM Processor)

C: x = (a + b) - c;

Assembler:ADR r4,a ; get address for aLDR r0,[r4] ; get value of aADR r4,b ; get address for b, reusing r4LDR r1,[r4] ; get value of bADD r3,r0,r1 ; compute a+bADR r4,c ; get address for cLDR r2,[r4] ; get value of c

© 2000 Morgan Kaufman

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C assignment, cont’d.

SUB r3,r3,r2 ; complete computation of xADR r4,x ; get address for xSTR r3,[r4] ; store value of x

© 2000 Morgan Kaufman

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Example: C assignments (SHARC DSP)

C:x = (a + b) - c;

Assembler:R0 = DM(_a) ! Load aR1 = DM(_b); ! Load bR3 = R0 + R1;R2 = DM(_c); ! Load cR3 = R3-R2;DM(_x) = R3; ! Store result in x