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LAPORAN LABORATORIUM

PROGRAM STUDI BROADBAND MULTIMEDIA

02

GERBANG UNIVERSAL

 NAMA PRAKTIKAN : RIO PURCAHYANTO DWI SUNU

 NAMA REKAN KERJA : 1. DAVID ARLAS

  2. TALITHA ARIFANI

KELAS/KELOMPOK : BM-2/0

TANGGAL PELAKSANAAN PRAKTIKUM : 2! FEBRUARI 201!

TANGGAL PENYERAHAN LAPORAN : 0" MARET 201!

JURUSAN TEKNIK ELEKTRO

POLITEKNIK NEGERI JAKARTA

2! FEBRUARI 201!

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DAFTAR ISI

DAFTAR ISI....................................................................................................1

1. TUJUAN..............................................................................................2

2. DASAR TEORI...................................................................................2

2.1...................................................................................................NAND Gate

sebagai Inverter NOT Gate!.................................................2

2.2...................................................................................................NAND Gate

sebagai AND Gate...................................................................2

2."...................................................................................................NAND Gate

sebagai OR Gate....................................................................."2.#...................................................................................................NAND Gate

sebagai NOR Gate..................................................................."

2.$...................................................................................................NOR Gate

sebagai Inverter NOT Gate!.................................................#

2.%...................................................................................................NOR Gate

sebagai AND Gate...................................................................#

2.&...................................................................................................NOR Gate

sebagai OR Gate.....................................................................#

2.'...................................................................................................NOR Gate

sebagai NAND Gate................................................................$

". ALAT ( ALAT )ANG DI*ERGUNA+AN.......................................%

#. LANG+A, ( LANG+A, *ER-OBAAN.......................................%

#.1 NAND Gate sebagai Inverter NOT Gate!...........................%

#.2 NAND Gate sebagai AND Gate.............................................&

#." NAND Gate sebagai OR Gate................................................&

#.# NAND Gate sebagai NOR Gate.............................................&

#.$ NOR Gate sebagai Inverter NOT Gate!..............................'

#.% NOR Gate sebagai AND Gate................................................'

#.& NOR Gate sebagai OR Gate..................................................'#.' NOR Gate sebagai NAND Gate.............................................

$. *ERTAN)AAN DAN TUGAS...........................................................

%. DATA ,ASIL *ER-OBAAN............................................................

ANALISA DAN *E/BA,ASAN...........................................................12

*ERTAN)AAN DAN TUGAS.................................................................1$

+ESI/*ULAN.........................................................................................1%

DAFTAR *USTA+A................................................................................1&

1

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LA/*IRAN..............................................................................................1'

1. TUJUAN

• M#$%&'(%) NAND G%*# +#,%'%) '#$,%&' &)#$+% U&)#$+% G%*#

• M#$%&'(%) NOR G%*# +#,%'%) '#$,%&' &)#$+% U&)#$+% G%*#

2. DASAR TEORI

G#$,%&' &)#$+% %%%3 +%%3 +%* '#$,%&' %+%$ 4%&' )$%&'(%) +#3)&''%

5#&'3%+)(%& 6*7* 4%&' +%5% #&'%& '#$,%&' %+%$ %)&&4%. A%7& '#$,%&'

&)#$+% *#$+#,* %%%3 NAND G%*# %& N6$ G%*#.

2.1.  NAND Gate seagai Inverter NOT Gate!

 NOT G%*# %7%* ),%$ #&'%& 5#&''&%(%& NAND G%$# G%5,%$ 2.1.

B)% )&7* ),#$) 6')8 1 5%(% 6*7*&4% 5#&9%) 6')8 0 ,#')* 9'%

+#,%)(&4%.

2.2.  NAND Gate sebagai AND

Gate

AND G%*# %7%* ),%* #&'%& 5#&''&%(%& NAND G%*# G%5,%$ 2.2.

O*7* %$) +%* $%&'(%)%& AND G%*# %(%& ,#$%% 7%% (#%%%& 6')( 1

 9)(% %& 3%&4% 9)(% +#5% )&7*&4% 7%% (#%%%& 6')8 1. D%& 6*7* %(%&

 ,#$%% 7%% (#%%%& 6')( 0 %7%,)% +%%3 +%* )&7*&4% %*% +#5%&4%

 7%% (#%%%& 6')8 0.

2.".  NAND Gate sebagai

OR Gate

2

T%,# K#,#&%$%& :

I&7* A O*7* Y

0 1

1 0

I&7*O*7* Y

A B

0 0 0

0 1 0

1 0 0

1 1 1

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OR G%*# %7%* ),%* #&'%& 5#&''&%(%& NAND G%*# G%5,%$ 2.".

O*7* %$) +%* $%&'(%)%& OR G%*# %(%& ,#$%% 7%% 6')8 0 9)(% %&

3%&4% 9)(% +#5% )&7*&4% 7%% (#%%%& 0. D%& 6*7* %(%& ,#$%% 7%%

(#%%%& 6')8 1 %7%,)% +%%3 +%* )&7*&4% %*% +#5%&4% 7%% (#%%%&

6')8 1.

 

2.#. NAND Gate sebagai

NOR Gate

 NOR G%*# %7%* ),%* #&'%& 5#&''&%(%& NAND G%*# G%5,%$ 2..

 NOR G%*# %%%3 '%,&'%& %$) +%* $%&'(%)%& NOT G%*# 4%&' )7%+%&'

 7%% ,%')%& 6*7* $%&'(%)%& OR G%*#. O*7* %$) 6')8 1 9)(% %& 3%&4%

 9)(% +#5% )&7*&4% ,#$%% 7%% (#%%%& 0. D%& 6*7*&4% 0 %7%,)% +%%3+%* %*% +#5% )&7*&4% ,#$%% 7%% 6')8 1.

2.$.  NOR Gate sebagai Inverter NOT Gate!

 NOT G%*# %7%* ),%* #&'%& 5#&''&%(%& NOR G%*#. B)% )&7* ),#$)

6')8 1 5%(% 6*7*&4% 5#&9%) 6')8 0 ,#')* 9'% +#,%)(&4%.

3

I&7*O*7* Y

A B

0 0 0

0 1 1

1 0 1

1 1 1

I&7*O*7* Y

A B

0 0 1

0 1 0

1 0 0

1 1 0

T%,# K#,#&%$%& :

I&7* A O*7* Y

0 1

1 0

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2.%.  NOR Gate sebagai AND Gate

AND G%*# %7%* ),%* #&'%& 5#&''&%(%& NOR G%*#. O*7* %$) +%*

$%&'(%)%& AND G%*# %(%& ,#$%% 7%% (#%%%& 6')( 1 9)(% %& 3%&4% 9)(%

+#5% )&7*&4% 7%% (#%%%& 6')8 1. D%& 6*7* %(%& ,#$%% 7%%

(#%%%& 6')( 0 %7%,)% +%%3 +%* )&7*&4% %*% +#5%&4% 7%% (#%%%&

6')8 0.

2.&.  NOR Gate sebagai OR 

Gate

OR G%*# %7%* ),%* #&'%& 5#&''&%(%& OR G%*#. O*7* %$) +%*

$%&'(%)%& OR G%*# %(%& ,#$%% 7%% 6')8 0 9)(% %& 3%&4% 9)(% +#5%

)&7*&4% 7%% (#%%%& 0. D%& 6*7* %(%& ,#$%% 7%% (#%%%& 6')8 1

%7%,)% +%%3 +%* )&7*&4% %*% +#5%&4% 7%% (#%%%& 6')8 1.

4

I&7*O*7* Y

A B

0 0 0

0 1 0

1 0 0

1 1 1

I&7*O*7* Y

A B

0 0 0

0 1 1

1 0 1

1 1 1

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2.'.  NOR Gate sebagai NAND Gate

 NAND G%*# %7%* ),%* #&'%& 5#&''&%(%& NOR G%*#. NAND G%*#

%%%3 '%,&'%& %$) +%* $%&'(%)%& NOT G%*# 4%&' )7%+%&' 7%% ,%')%&

6*7* $%&'(%)%& AND G%*#. O*7* %$) 6')8 1 9)(% %& 3%&4% 9)(% +#5%

)&7*&4% ,#$%% 7%% (#%%%& 0. D%& 6*7*&4% 0 %7%,)% +%%3 +%* %*%

+#5% )&7*&4% ,#$%% 7%% 6')8 1.

". ALAT ( ALAT )ANG DI*ERGUNA+AN

 N6. A%* ; %%* %& (6576& J5%3

1IC

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#. LANG+A, ( LANG+A, *ER-OBAAN

L%&'(%3 ; %&'(%3 %%5 5#%((%& 7#$86,%%& '#$,%&' &)#$+% %%%3 +#,%'%)

 ,#$)(*

#.1 NAND Gate sebagai Inverter NOT Gate!

1. L)3%* data sheet &*( IC #$ +774 +#,#+%$ ? 6* #&'%& 8%$% 5#&'3,&'(%&

*#$5)&% ; *#$5)&% 7%% 76>#$ +774 #&'%& *#$5)&%4%&' %% 7%%

5*)5#*#$.

". B%* $%&'(%)%& +#7#$*) '%5,%$ .1

. B#$)(%& 6')8 0 %&/ %*% 1 7%% )&7* A +#+%) *%,# !.1

?. A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. 8%*%* 3%+)&4% 7%% *%,#

!.1

#.2 NAND Gate sebagai AND Gate

1. B%* $%&'(%)%& +#7#$*) '%5,%$ .2

2. B#$)(%& 6')8 1 %&/ %*% 0 7%% 5%+)&'-5%+)&' )&7* A %& )&7* B

+#+%) *%,# !.2

". A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. 8%*%* 3%+) ; 3%+)&4% 7%% *%,# !.2

#." NAND Gate sebagai OR Gate

1. B%* $%&'(%)%& +#7#$*) '%5,%$ ."

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2. B#$)(%& 6')8 1 %&/ %*% 0 7%% 5%+)&'-5%+)&' )&7* A %& )&7* B

+#+%) *%,# !."

". A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. 8%*%* 3%+) ; 3%+)&4%

 7%% *%,# !."#.# NAND Gate sebagai NOR Gate

1. B%* $%&'(%)%& +#7#$*) '%5,%$ .

2. A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. 8%*%* 3%+) ; 3%+)&4%

 7%% *%,# !.

". A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. 8%*%* 3%+) ; 3%+)&4%

 7%% *%,# !.

#.$ NOR Gate sebagai Inverter NOT Gate!

1. B%* $%&'(%)%& +#7#$*) '%5,%$ .?

2. B#$)(%& L6')( 0 %&/%*% 1 7%% 5%+)&' ; 5%+)&' )&7* A %& B +#+%)

*%,# !.?

". A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. C%*%* 3%+)&4% 7%% *%,#

!.?

#.% NOR Gate sebagai AND Gate

1. B%* $%&'(%)%& +#7#$*) '%5,%$ .!

2. B#$)(%& L6')( 0 %&/%*% 1 7%% 5%+)&' ; 5%+)&' )&7* A %& B +#+%)

*%,# !.!

". A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. C%*%* 3%+)&4% 7%% *%,#

!.!

#.& NOR Gate sebagai OR Gate

1. B%* $%&'(%)%& +#7#$*) '%5,%$ .<

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2. B#$)(%& L6')( 0 %&/%*% 1 7%% 5%+)&' ; 5%+)&' )&7* A %& B +#+%)

*%,# !.<

". A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. C%*%* 3%+)&4% 7%% *%,#

!.<

#.' NOR Gate sebagai NAND Gate

1. B%* $%&'(%)%& +#7#$*) '%5,%$ 

2. B#$)(%& L6')( 0 %&/%*% 1 7%% 5%+)&' ; 5%+)&' )&7* A %& B +#+%)

*%,# !.

". A5%*) LED +#$*% ($ *#'%&'%& 7%% 6*7* Y. C%*%* 3%+)&4% 7%% *%,#

!.

$. *ERTAN)AAN DAN TUGAS

1. A7%(%3 NOR G%*# *#$5%+( '#$,%&' &)#$+%

2. D%7%*(%3 E-OR G%*# ),%* %$) $%&'(%)%& NAND G%*# 9#%+(%&

". B%*%3 $%&'(%)%& 6')(% NOT G%*# AND G%*# NAND G%*# %& OR G%*#

%$) $%&'(%)%& NOR G%*#

. B%*%3 (#+)57%& %$) 7#$86,%%& )&)

%. DATA ,ASIL *ER-OBAAN

Tabe %.1. NAND Gate sebagai Inverter NOT Gate!

Int Ott

A ) V3t!

0 1 "202

1 0 00!

Tabe %.2. NAND Gate sebagai AND Gate

Int Ott

8

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A B ) V3t!

0 0 0 00

0 1 0 00

1 0 0 00

1 1 1 "2

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Int Ott

A B ) V3t!

0 0 0 010

0 1 0 0120

1 0 0 01201

1 1 1 ""!

Tabe %.& NOR Gate sebagai OR Gate

Int Ott

A B ) V3t!

0 0 0 010!

0 1 1 "

1 0 1 ""

1 1 1 "

Tabe %.' NOR Gate sebagai NAND Gate

Int Ott

A B ) V3t!

0 0 1 ""!

0 1 1 ""!

1 0 1 ""!

1 1 0 010?

&. ANALISA DAN *E/BA,ASAN

&.1 NAND Gate sebagai InverterNOT Gate!

B#$%+%$(%& *#6$) %7%,)% 6')8 0 5%+( (# '#$,%&' NOT 5%(%

6*7* 5#&9%) 6')8 1 %& +#,%)(&4%. I&7* %(%& 5%+( (# (#% )&7*

'#$,%&' NAND %& (#%$ +#,%'%) 6*7* %$) NAND. D#&'%& )&7* 0 +%%*

10

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5%+( (# '#$,%&' NAND 5%(% (#% )&7* '#$,%&' NAND 5#5))() 6')8

0 %& (#%$ +#,%'%) 1 #&'%& *#'%&'%& +#,#+%$ "202 V6*. S%%* )&7* 1

5%+( 5%(% (#% )&7* NAND %(%& 5#5))() 6')8 1 %& 6*7* %(%&

5#5))() 6')8 0 #&'%& *#'%&'%& *#$($ 7%% 5*)5#*#$ +#,#+%$ 00!

6*.

&.2 NAND Gate sebagai AND Gate

B#$%+%$(%& *#6$) ) %*%+ )&7* %(%& 5%+( (# '#$,%&' NAND

 7#$*%5% %& 6*7* %$) '#$,%&' NAND 7#$*%5% %(%& 5%+( +#,%'%) )&7*

&*( '#$,%&' NAND (#% %& 6*7*&4% %%%3 6*7* 4%&' +#,#&%$&4%.

+%%* )&7* A 0 %& B 0 5%(% 6*7*&4% %%%3 0 %& *#$($ 7%%

5*)5#*#$ +#,#+%$ 00 V6*. S%%* )&7* A 0 %& B 1 6*7*&4% %%%3

0 #&'%& *#'%&'%& +#,#+%$ 0 V6*. S%%* )&7* A 1 %& B 0 5%(%

6*7*&4% %%%3 0 #&'%& *#'%&'%& +#,#+%$ 0 V6*. S%%* )&7* A 1 %&

B 1 5%(% 6*7*&4% %%%3 1 #&'%& *#'%&'%& *#$($ +#,#+%$ "

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%& %$) B 1 5%(% 6*7* 4%&' )%7%* %%%3 0 %& %(%& 9%) )&7* &*( 

5%+( %') +#,%'%) )&#$*#$ %& 6*7* %(%& 5#&'#%$(%& 6')8 1.

I&7* %)& 7& 7$6+#+&4% %(%& +%5%. S%%* )&7* A 0 %& B 1 5%(%

6*7*&4% %%%3 0 #&'%& *#'%&'%& +#,#+%$ 01

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5%+( (#5,%) +#,%'%) )&7* U12 G#$,%&' NOR 7#$*#5%& %$) )&7* A

%& B. 7%% )&7* B 5%+( (# '#$,%&' U11 '#$,%&' NAND 7#$*%5% 7%%

)&7* B %& 6*7*&4% %(%& 5#&9%) )&7* &*( U12. I&7* A %& B %(%&

5%+( (# U12 %& 6*7*&4% %(%& 5%+( (# U1 %& %(%& ) )&#$*. I&)

%%%3 6*7* %$) $%&'(%)%& *#$+#,*. P%% +%%* )&7* A 0 %& B 0

5%(% 6*7*&4% %%%3 1 #&'%& *#'%&'%& +#,#+%$ ""! V6*. P%% +%%*

)&7* A 0 %& B 1 5%(% 6*7*&4% %%%3 1 #&'%& *#'%&'%%& +#,#+%$ 

""! V6*. P%% +%%* A 1 %& B 0 5%(% 6*7*&4% %%%3 1 #&'%&

*#'%&'%& +#,#+%$ ""! V6*. P%% +%%* )&7* A 1 %& B 1 6*7*&4%

%%%3 0 #&'%& *#'%&'%& +#,#+%$ 010?.

*ERTAN)AAN DAN TUGAS

1. A7%(%3 NOR G%*# *#$5%+( '#$,%&' &)#$+% J#%+(%&

Y% +#7#$*) NAND G%*# NOR G%*# 7& %7%* )9%)(%& '#$,%&' &)#$+%

(%$#&% #&'%& )$%&'(%) +##5)()%& $7% 5%(% ,)+% )%7%*(%& 6*7* #&'%&

3%+) 4%&' +%5% #&'%& '#$,%&' %+%$.

2. D%7%*(%3 E-OR G%*# ),%* %$) $%&'(%)%& NAND G%*# 9#%+(%&

Y% #&'%& '#$,%&' 6')(% NAND G%*# +#7#$*) '%5,%$ ),%>%3 5%(% ()*% ,)+%

5#5,%* 6*7* +#7#$*) E-OR G%*#.

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+ESI/*ULAN

G#$,%&' &)#$+% %%%3 +%%3 +%* '#$,%&' %+%$ 4%&' )$%&'(%) %&

5#&'3%+)(%& 6*7* 4%&' +%5% #&'%& '#$,%&' %+%$. G#$,%&' &)#$+%

*#$+#,* %%%3 NAND G%*# %& NOR G%*#.

G#$,%&' NAND G%*# %7%,)% )$%&'(%) +##5)()%& $7% ,)+%

5#&'3%+)(%& $%&'(%)%& 4%&' ,)+% 5#&'#%$(%& 6*7* 4%&' +%5% #&'%&

'#$,%&' 6')(% %+%$. S#3)&''% ,)+% 5#&'3#5%* %& 5#5%(+)5%(%& 7#&''&%%&

IC

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DAFTAR *USTA+A

 N)6& B#&&4. 200.  Diktat Laboratorium Digital 1 (Rangkaian Kombinatorial).

P6)*#(&)( N#'#$) J%(%$*%

W)9%&%$(%W)9%4%. 200!. Teknik Digital. P#$,)* E$%&''%: J%(%$*%.

A&6&)5. Gerbang Logika. 2 M%$#* 201!.

3**7+://).>)()7#)%.6$'/>)()/G#$,%&'6')(% 

15

https://id.wikipedia.org/wiki/Gerbang_logikahttps://id.wikipedia.org/wiki/Gerbang_logikahttps://id.wikipedia.org/wiki/Gerbang_logika

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LA/*IRAN

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