Dell Inspiron 1545 - Wistron Dr1 Roberts Uma - 48.4aq01.031 08212-3

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

Roberts -3Cover Page

Custom

1 59Monday, August 03, 2009

Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


Intel Cantiga-GM + ICH9M

2009-08-03

REV : -3

DR1(Roberts) Schematics Document

uFCPGA Mobile Penryn

DY : Nopop Component

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Roberts -3Block Diagram

Custom

2 59Thursday, August 27, 2009

Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


EMC2102

FSB800/1066MHz

DMIx4

KBC

Thermal & Fan Int. KB

LPC Bus

2MBFlash ROM

Intel Mobile CPU

DDRII667/800

DDRII667/800

Slot 0

Slot 1

DDRII 667/800 Channel A

DDR II 667/800 Channel B

Roberts Block Diagram

LVDS(Dual Channel)

CRT(on I/O board)

LCD

RGB CRT

Penryn

Cantiga-GMLAGTL+ CPU I/F

External GraphicsDDR Memory I/F

ICH9-MUSB 2.0/1.1 ports (12)

SATA ports (4)High Definition Audio

ACPI 1.1LPC I/F

PCI/PCI BRIDGE

PCI Express ports (6)

WINBONDWPCE773L

SPI

5,6,7

8,9,10,11,12,13

14

1535

Clock GeneratorSLG8SP513VTR

24

4

42 44 25

16,17,18,19

TouchPAD

44

PCB LAYER

L3: SignalL2: VCC

L5: GNDL4: Signal

L6: Bottom

L1: Top

Project code : 91.4AQ01.001PCB P/N : 48.4AQ01.031Revision : 08212-3

C-LINK

26

27

+3.3V_RTC_LDO

28,29

30

31

+0.9V_DDR_VTT

32

ISL6266AOUTPUTS+VCC_CORE

INPUTS+PWR_SRC

CPU DC/DC

OUTPUTS+V_DDR_MCH_REF

TPS51116SYSTEM DC/DC

INPUTS+1.8V_SUS

+3.3V_ALW

OUTPUTS+5V_ALW+PWR_SRC

MAX17020INPUTS

SYSTEM DC/DC

OUTPUTS+1.05V_VCCP

TPS51117SYSTEM DC/DCINPUTS+PWR_SRC

OUTPUTS+1.5V_RUN+1.8V_SUS

APL5912INPUTS

SYSTEM DC/DC

OUTPUTS+PWR_SRC

MAXIM CHARGERINPUTS

MAX8731A

+DC_IN

+5V_ALW2

+PBATT41Bluetooth

41

USB 2.0 x 1

PCIE

2010/100 NICMarvell 88E8040

PCIE x 1

Left Side:USB x 2

Right Side:USB x 1

CAMERA(Option) 41

43

USB 2.0 x 1

USB 2.0 x 1

USB 2.0

802.11a/b/g 37Mini-Card

41

41New Card

PCIE x 1

G577BR91UPower SW

RJ45CONN

PCIE x 1 & USB 2.0 x 1

Intel

Intel

Socket P

ODD

S

A

T

A

36 36

S

A

T

A

HDD

RealtekRTS5159

CardReader

21

SD/MMCMS/MS Pro/xD

37

USB2.0

AzaliaCODEC IDT92HD71B7

AZALIA

23

OP AMPMAX9789A

22

2CH SPEAKER

MIC IN

HP1

Internal Analog MIC

Digital Mic Array

34

+5V_RUNOUTPUTS+3.3V_RUN

LDOSYSTEM DC/DC

INPUTS+5V_ALW+3.3V_ALW

USB 2.0 x 2 I/

O

B

o

a

r

d

C

o

n

n

e

c

t

o

r

+PWR_SRC

CAMERA Module

40

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


Roberts -3Table of Content

Custom

3 59Monday, May 18, 2009

Title


Date: Sheet of



Custom

3 59Monday, May 18, 2009

Title


Date: Sheet of



Custom

3 59Monday, May 18, 2009

CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered inOrder1 = Reverse LanesDMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)DMI x2 mode [MCH->ICH]: (3->0, 2->1)

Pair Device01234567891011

HDA_SDOUTSignal

XOR Chain Entrance/PCIE Port Config1 bit1,Rising Edge of PWROK.

Usage/When SampledAllows entrance to XOR Chain testing when TP3pulled low. When TP3 not pulled low at rising edgeof PWROK, sets bit1 of RPC.PC (Cofig Registers:offset 224h). This signal has weak internal pull-down.

Comment

SATALED# PCI Express LaneReversal. Rising Edgeof PWROK.

Signal has weak internal pull-up. Sets bit 27of MPC.LR (Device 28: Function 0:Offset D8).

SPKR No Reboot.Rising Edge of PWROK.If sampled high, the system is strapped to the"No Reboot" mode (ICH9 will disable the TCO Timersystem reboot feature). The status is readablevia the NO REBOOT bit.

TP3 XOR Chain Entrance.Rising Edge of PWROK.

The pull-up or pull-downactive when configured for native GLAN_DOCK#functionality and determinedby LAN controller.

CFG6 iTPM Host Interface 1 = The iTPM Host Interface is disabled (default)CFG7 Intel Management

engine crypto strap

CFG9

0 = Transport Layer Security (TLS) cipher

CFG20 Digital Display Port(SDVO/DP/iHDMI)Concurrent with PCIe

0 = Only Digital Display Port or PCIE isoperational (Default)1 = Digital display Port and PCIe are operatingsimulataneously via the PEG portSDVO_CTRLDATA

SDVO Present 0 = No SDVO Card Present (Default)

ICH9 EDS 642879 Rev.1.5

HDA_SYNC PCIE config1 bit0,Rising Edge of PWROK.

This signal has a weak internal pull-down.Sets bit0 of PRC.PC (Config Registers: Offset 224h).

GNT2#/GPIO53

PCIE config2 bit2,Rising Edge of PWROK.

This signal has a weak internal pull-up.Sets bit2 of PRC.PC2 (Config Registers: Offset 224h).

GPIO20 Reserved.

This signal should not be pull low unless usingXOR Chain testing.

GPIO33/HDA_DOCK_EN#

Flash DescriptorSecurity Override Strap. Rising Edge of PWROK.

Sampled low: the Flash Descriptor Security will beoverridden. If high, the security measures will bein effect. This should only be enabled inmanufacturing environments using an external pull-up resister.

Cantiga chipset and ICH9M I/O controllerHub strapping configuration

suite with no confidentiality1 = TLS cipher suite with confidentiality(Default)PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 14->1 ect..1 = Normal operation (Default): Lane Numbered inOrder

1 = SDVO Card PresentL_DDC_DATA Local Flat Panel

(LFP) Present0 = LFP Disabled (Default)1 = LFP Card Present; PCIE disabled

USB1USB2

RESERVED

Card Reader

MINI CARD

BLUETOOTH

USB3

CAMERA

NEW CARD

RESERVED

RESERVED

RESERVED

PULL-DOWN 20K

PULL-DOWN 20K

GPIO49

PULL-UP 20K

ICH9M Functional Strap Definitions ICH9 Integrated pull-upand pull-down ResistorsSIGNAL Resistor Type/Value

HDA_BIT_CLK

HDA_RST#HDA_SDIN[3:0]HDA_SDOUTHDA_SYNC

GNT[3:0]#/GPIO[55,53,51]GPIO20

LDA[3:0]#/FHW[3:0]#

LDRQ[0]

PME#PWRBTN#SATALED#

LAN_RXD[2:0]

LDRQ[1]/GPIO23

TP[3]

SPKR

SPI_CS1#/GPIO58/CLGPIO6

USB[11:0][P,N]

SPI_MOSISPI_MISO

TACH_[3:0]PULL-DOWN 20K

PULL-DOWN 15K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20KPULL-UP 20KPULL-UP 20KPULL-UP 20KPULL-UP 15KPULL-UP 20KPULL-DOWN 20KPULL-UP 20K

PULL-UP 20KPULL-UP 20K

PULL-DOWN 20KPULL-DOWN 20KPULL-DOWN 20KPULL-DOWN 20K

This signal should not be pulled high.GNT1#/GPIO51

ESI Strap (Server Only)Rising Edge of PWROK.

ESI compatible mode is for server platforms only.This signal should not be pulled low for desktopand mobile.

GNT3#/GPIO55

Top-Block Swap override. Rising Edgeof PWROK.

Sampled low: Top-Block Swap mode (inverts A16 forall cycles targeting FWH BIOS space).Note: Software will not be able to clear theTop-Swap bit until the system is rebootedwithout GNT3# being pulled down.

GNT0#:SPI_CS1#/GPIO58

ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 Rev.0.5

CFG10 PCIE Loopback enable 0 = Enable (Note 3)1 = Disable (Default)CFG[13:12] XOR/ALL

NOTE:1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.

CL_CLK[1:0]CL_DATA[1:0]CL_RST0#DPRSLPVR/GPIO16ENERGY_DETECT

HDA_DOCK_EN#/GPIO33

011 = FSB667010 = FSB800others = ReservedCFG[4:3]CFG[15:14]CFG[18:17]

00 = Reserve10 = XOR mode Enabled01 = ALLZ mode Enable (Note 3)11 = Disabled (Default)CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled1 = Dynamic ODT Enabled (Default)Boot BIOS Destination

Selection 0:1.Rising Edge of PWROK.

Controllable via Boot BIOS Destination bit(Config Registers: Offset 3410h:bit 11:10).GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC

SPI_MOSI Integrated TPM Enable,Rising Edge of CLPWROK.

Sample low: the Integrated TPM will be disable.Sample high: the MCH TPM enable strap is sampledlow and the TPM Disable bit is clear, theIntegrated TPM will be enable.

GLAN_DOCK#

PULL-UP 20K

PULL-DOWN 20KPULL-UP 20K

PULL-UP 20KPULL-UP 20KPULL-UP 20K

Pin Name

USBUSB TablePCIE Routing

LANE2LANE3 LAN

MiniCard WLAN

GPIO49 DMI TerminationVoltage. Rising Edgeof CLPWROK.

The signal is required to be low for desktopapplications and required to be high for mobileapplications.

Strap Description Configuration

0 = The iTPM Host Interface is enabled (Note 2)

CFG[2:0] FSB Frequency Select 000 = FSB1067

CFG8 Reserved

CFG5 DMI x2 Select 0 = DMI x21 = DMI x4 (Default)

LANE5 New Card

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_MCH_DREFCLK

NEWCARD_CLKREQ#

CLK_MCH_DREFCLK#

PCI2_TME

FSB

FSA

PCI2_TME

FSC

CLK_XTAL_OUT

27_SEL

27_SEL

ITP_EN

FSB

FSA

FSC

ITP_EN

CLK_XTAL_IN

CLK_PCIE_NEWCLK_PCIE_NEW#

CLKREQ#_1

NEWCARD_CLKREQ#MINI1_CLKREQ#

+3.3V_RUN 3D3V_S0_CK505

3D3V_S0_CK505_IO

3D3V_S0_CK505

3D3V_S0_CK505_IO3D3V_S0_CK505+3.3V_RUN

3D3V_S0_CK505

+3.3V_RUN

CLK_CPU_BCLKCLK_CPU_BCLK#

CLK_MCH_BCLK#CLK_MCH_BCLK

MCH_SSCDREFCLK#MCH_SSCDREFCLK

CLK_MCH_DREFCLK#CLK_MCH_DREFCLK

NEWCARD_CLKREQ#

CLK_48M_ICH

H_STP_PCI#H_STP_CPU#

ICH_SMBCLKICH_SMBDATA

CK_PWRGD

CLKSATAREQ#CLKREQ#_B

PCLK_KBCCLK_PCI_ICH

CLK_14M_ICH

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

MCH_CLKSEL0

MCH_CLKSEL1

MCH_CLKSEL2

CLK_PCIE_NEW#CLK_PCIE_NEW

CLK_PCIE_ICH#CLK_PCIE_ICH

CLK_MCH_3GPLL#CLK_MCH_3GPLL

CLK_PCIE_SATA#CLK_PCIE_SATA

CLK_PCIE_LANCLK_PCIE_LAN#

PCLK_FWH

CLK_CPU_ITP#CLK_CPU_ITP

CLK_48M_CARD

CLK_PCIE_MINI1#CLK_PCIE_MINI1

MINI1_CLKREQ#

Title


Date: Sheet of


Roberts -3Clock Generator SLG8SP513VTR

Custom

4 59Tuesday, August 11, 2009

Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


GM45PM45

PCI2_TME Output

0

1

Overclocking of CPU and SRC allowed

Overclocking of CPU and SRC not allowed 27_SEL PIN 20 PIN 21

ITP_EN Output

0 SRC81 CPU_ITP

SSID = CLOCK

SEL1FSB

SEL0FSA

133M100M

166M800M

0 101 X

667M200M

0 1

CPUSEL2FSC FSB

0 10

101

1067M266M0 0 0

533M

Main source: 71.08513.003 (SLG8SP513VTR) 2nd source: 71.00875.C03 (RTM875N-606-VD-GRT) 3rd source: Co-layout Ref: 71.09355.B03 (ICS9LPRS355BKLFT)

0 DOT96T DOT96C 1 SRCT0 SRCC0

A00.08/0910

A00.08/0910

A00.08/0922

SB

1 2R196 33R2J-2-GPDYR196 33R2J-2-GPDY

1 2R2040R0603-PAD

R2040R0603-PAD

1 2R193 10KR2J-3-GPR193 10KR2J-3-GP

1

2

C

2

1

0

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

1

0

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

2

1

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

1

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1 2R190 33R2J-2-GPR190 33R2J-2-GP

1

2

C461SC12P50V2JN-3GP

C461SC12P50V2JN-3GP

1

2

R21810KR2J-3-GPDY R21810KR2J-3-GPDY

1 2R214 2K2R2J-2-GPR214 2K2R2J-2-GP

1

2

C

2

3

4

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

3

4

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

2

0

9

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

0

9

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

2

1

1

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

C

2

1

1

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

1 2R178 475R2F-L1-GPR178 475R2F-L1-GP

1

2

C

2

2

9

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

2

2

9

S

C

1

U

1

0

V

3

K

X

-

3

G

P

1

2

C

2

1

5

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

1

5

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

2

2

6

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

DY C 22

6

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

DY

1

2

C

2

2

5

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

2

5

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

2

3

9

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

3

9

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

4

6

4

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY C 46

4

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY

1 2R186 10KR2J-3-GPR186 10KR2J-3-GP

1

2

C

2

3

3

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

2

3

3

S

C

1

U

1

0

V

3

K

X

-

3

G

P

1 2X3

X-14D31818M-37GP

X3

X-14D31818M-37GP

1

2

C

2

0

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

0

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

G

N

D

R

E

F

1

X22X13

V

D

D

R

E

F

4

REF0/FSLC/TEST_SEL5

SDATA6SCLK7

PCI0/CR#_A8

V

D

D

P

C

I

9

PCI1/CR#_B10PCI2/TME11PCI312PCI4/27_SELECT13PCI_F5/ITP_EN14

G

N

D

P

C

I

1

5

V

D

D

4

8

1

6

USB_48MHZ/FSLA17

G

N

D

4

8

1

8

V

D

D

9

6

_

I

O

1

9

SRCT0/DOTT_96 20SRCC0/DOTC_96 21

G

N

D

2

2

V

D

D

P

L

L

3

2

3

27MHZ_NONSS/SRCT1/SE1 2427MHZ_SS/SRCC1/SE2 25

G

N

D

2

6

V

D

D

P

L

L

3

_

I

O

2

7

SRCT2/SATAT 28SRCC2/SATAC 29

G

N

D

S

R

C

3

0

SRCT3/CR#_C 31SRCC3/CR#_D 32

V

D

D

S

R

C

_

I

O

3

3

SRCT4 34SRCC4 35

G

N

D

S

R

C

3

6

SRCT9 37SRCC9 38

SRCC11/CR#_G 39SRCT11/CR#_H 40

SRCT10 41SRCC10 42

V

D

D

S

R

C

_

I

O

4

3

CPU_STOP#44PCI_STOP#45

V

D

D

S

R

C

4

6

SRCC6 47SRCT6 48

G

N

D

S

R

C

4

9

SRCC7/CR#_E 50SRCT7/CR#_F 51

V

D

D

S

R

C

_

I

O

5

2

CPUC2_ITP/SRCC8 53CPUT2_ITP/SRCT8 54

NC#5555

V

D

D

C

P

U

_

I

O

5

6

CPUC1_F 57CPUT1_F 58

G

N

D

C

P

U

5

9

CPUC0 60CPUT0 61V

D

D

C

P

U

6

2

CK_PWRGD/PD#63

FSLB/TEST_MODE64

G

N

D

6

5

U54

ICS9LPRS355BKLFT-GP-U

U54

ICS9LPRS355BKLFT-GP-U

1

2

C

2

3

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

3

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

2

4

3

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY C 24

3

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY

1 2R212 33R2J-2-GPR212 33R2J-2-GP

1 2R217 22R2J-2-GPR217 22R2J-2-GP

1

2

E

C

5

7

S

C

2

2

P

5

0

V

2

J

N

-

4

G

P

E

C

5

7

S

C

2

2

P

5

0

V

2

J

N

-

4

G

P

1

2

R19810KR2J-3-GPR19810KR2J-3-GP

1 2R216

22R2J-2-GP

R216

22R2J-2-GP

1 2R215 1KR2J-1-GPR215 1KR2J-1-GP

1 2C245 SC4D7P50V2CN-1GPDYC245 SC4D7P50V2CN-1GPDY

1 2R195 10KR2J-3-GPR195 10KR2J-3-GP

1 2R207 33R2J-2-GPR207 33R2J-2-GP

1

2

C

2

3

6

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY C 23

6

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY

1

2

C

4

6

3

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY C 46

3

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY

1 2R411 1KR2J-1-GPR411 1KR2J-1-GP

1 2R2000R0603-PAD

R2000R0603-PAD

1

2


1

2

R20210KR2J-3-GPDYR20210KR2J-3-GPDY

1

2


1

2

C462SC12P50V2JN-3GP

C462SC12P50V2JN-3GP

1

2

C

2

2

4

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY C 22

4

S

C

4

D

7

P

5

0

V

2

C

N

-

1

G

P

DY

1

2

C

2

3

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

2

3

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

EC140SC47P50V2JN-3GPDY EC140SC47P50V2JN-3GPDY

1 2R181 1KR2J-1-GPR181 1KR2J-1-GP

1 2R4120R0402-PAD

R4120R0402-PAD

1

2

EC139SC47P50V2JN-3GPDY EC139SC47P50V2JN-3GPDY

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_A#3H_A#4H_A#5H_A#6H_A#7H_A#8H_A#9H_A#10H_A#11H_A#12H_A#13H_A#14H_A#15H_A#16

H_REQ#0H_REQ#1H_REQ#2H_REQ#3H_REQ#4

H_A#[35..3]

ITP_TCKITP_TDI

ITP_TMSITP_TRST#

ITP_TDO

ITP_DBRESET#

ITP_BPM#5

RSVD_CPU_4

RSVD_CPU_1

RSVD_CPU_8

RSVD_CPU_5RSVD_CPU_6RSVD_CPU_7

RSVD_CPU_2RSVD_CPU_3

H_A#35

H_A#33

RSVD_CPU_9RSVD_CPU_10

H_A#18

H_A#20H_A#21H_A#22

H_A#17

H_A#19

H_A#23H_A#24H_A#25H_A#26H_A#27H_A#28H_A#29H_A#30H_A#31

H_RS#1H_RS#0

H_RS#2

H_CPURST#

RSVD_CPU_11

H_A#34

H_A#32

CPU_IERR#

ITP_BPM#0ITP_BPM#1ITP_BPM#2ITP_BPM#3ITP_BPM#4

H_THERMDC

H_THERMDA

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_RS#[2..0]

H_ADSTB#1

H_FERR#H_IGNNE#

H_A20M#

H_LOCK#

H_INIT#

H_ADS#H_BNR#

H_DRDY#H_DBSY#

H_BREQ#0

H_BPRI#

H_DEFER#

H_STPCLK#H_INTRH_NMIH_SMI#

H_HIT#H_HITM#

H_TRDY#

H_ADSTB#0H_REQ#[4..0]

H_A#[35..3]

H_CPURST#

H_THRMTRIP#

CLK_CPU_BCLKCLK_CPU_BCLK#

H_THERMDAH_THERMDC

CPU_PROCHOT#

ITP_BPM#0ITP_BPM#1ITP_BPM#2ITP_BPM#3ITP_BPM#4ITP_BPM#5ITP_TCKITP_TDI

ITP_TDOITP_TMSITP_TRST#ITP_DBRESET#

Title


Date: Sheet of


Roberts -3CPU-FSB(1/3)

Custom


Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


H_THRMTRIP# should connect toICH9 and MCH without T-ing.

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

TEST7

62.10040.221

SSID = CPU

A00.08/0903

1 2R50 0R2J-2-GPDYR50 0R2J-2-GPDY

1TP34TP34

1TP31TP31

1TP12TP12

1TP24TP24

1 2R47 56R2J-4-GPR47 56R2J-4-GP

1TP30TP30

1TP23TP23

1 2R51 56R2J-4-GPR51 56R2J-4-GP

1TP19TP19

1TP25TP25

1TP13TP13

1

2

C49SC2200P50V2KX-2GPDY C49SC2200P50V2KX-2GPDY

1TP55TP55

1TP21TP21

1 2R76 56R2J-4-GPDYR76 56R2J-4-GPDY

A3#J4A4#L5A5#L4A6#K5A7#M3A8#N2A9#J1A10#N3A11#P5A12#P2A13#L2A14#P4A15#P1A16#R1

A20M#A6

ADS# H1

ADSTB0#M1

REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L1

A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5

A30#U2

A24#R4A25#T5A26#T3

A32#W3

A28#W5A29#Y4

A27#W2

A31#V4

A33#AA4A34#AB2A35#AA3

FERR#A5IGNNE#C4

RSVD#M4M4RSVD#N5N5RSVD#T2T2RSVD#V3V3RSVD#B2B2RSVD#C3C3

BNR# E2BPRI# G5

DEFER# H5

DBSY# E1DRDY# F21

BR0# F1

IERR# D20INIT# B3

LOCK# H4

RS0# F3RS1# F4RS2# G3

TRDY# G2

HIT# G6HITM# E4

BPM0# AD4BPM1# AD3BPM2# AD1BPM3# AC4PRDY# AC2PREQ# AC1

TCK AC5TDI AA6

TDO AB3TMS AB5

TRST# AB6DBR# C20

PROCHOT# D21THRMDA A24

THERMTRIP# C7

BCLK0 A22BCLK1 A21

RSVD#D2D2

RSVD#F6F6RSVD#D3D3RSVD#D22D22

STPCLK#D5LINT0C6LINT1B4SMI#A3

A23#U1

ADSTB1#V1

RESET# C1

KEY_NCB1

THRMDC B25

1 OF 4

R

E

S

E

R

V

E

D

HCLK

THERMAL

ADDR GROUP 1

X

D

P

/

I

T

P

S

I

G

N

A

L

S

C

O

N

T

R

O

L

ADDR GROUP 0ICH

U41A

BGA479-SKT6-GPU7

1 OF 4

R

E

S

E

R

V

E

D

HCLK

THERMAL

ADDR GROUP 1

X

D

P

/

I

T

P

S

I

G

N

A

L

S

C

O

N

T

R

O

L

ADDR GROUP 0ICH

U41A

BGA479-SKT6-GPU7

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39

H_D#41H_D#40

H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47

TEST1TEST2

COMP0COMP1COMP2COMP3

H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15

CPU_GTLREF0

H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31

H_D#48H_D#49

H_D#51H_D#50

H_D#52H_D#53H_D#54H_D#55

H_D#57H_D#56

H_D#58H_D#59H_D#60H_D#61

H_D#63H_D#62

H_D#[63..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_DINV#[3..0]

CPU_TEST3

CPU_TEST5

+1.05V_VCCP

H_DSTBN#2H_DSTBP#2H_DINV#2


H_DPRSTP#H_DPSLP#H_DPWR#H_PWRGOODH_CPUSLP#

H_D#[63..0]

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]



CPU_BSEL2

CPU_BSEL0CPU_BSEL1

PSI#

Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


Layout Note:Comp0, 2 connect with Zo=27.4 ohm, maketrace length shorter than 0.5".Comp1, 3 connect with Zo=55 ohm, maketrace length shorter than 0.5".

Layout notes Z= 55 Ohm 0.5" MAX for CPU_GTLREF0

Route the CPU_TEST3 and CPU_TEST5 signalsthrough a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

62.10040.221

SSID = CPU

D16#N22D17#K25D18#P26D19#R23D20#L23D21#M24D22#L22D23#M23D24#P25D25#P23D26#P22D27#T24D28#R24D29#L25D30#T25D31#N25

DINV0#H25

DINV1#N24

DSTBN0#J26

DSTBN1#L26

DSTBP0#H26

DSTBP1#M26

D0#E22D1#F24D2#E26D3#G22D4#F23D5#G25D6#E25D7#E23D8#K24D9#G24D10#J24D11#J23D12#H22D13#F26D14#K22D15#H23

D53# AC26

D60# AC22

D63# AC23

GTLREFAD26

TEST2D25

BSEL0B22BSEL1B23BSEL2C21

DINV2# U22

D32# Y22D33# AB24D34# V24D35# V26D36# V23

D38# U25D39# U23D40# Y25D41# W22D42# Y23D43# W24D44# W25D45# AA23D46# AA24D47# AB25

DSTBP2# AA26DSTBN2# Y26

D48# AE24D49# AD24

D52# AB21

D54# AD20D55# AE22D56# AF23D57# AC25D58# AE21D59# AD21

D61# AD23

DINV3# AC20

DSTBN3# AE25

D51# AB22D50# AA21

D62# AF22

COMP0 R26COMP1 U26

DPRSTP# E5DPSLP# B5DPWR# D24

PWRGOOD D6SLP# D7PSI# AE6

TEST1C23

TEST6A26

TEST3C24

TEST5AF1TEST4AF26

D37# T22

DSTBP3# AF24

COMP2 AA1COMP3 Y1

2 OF 4

DATA GRP0DATA GRP1

D

A

T

A

G

R

P

2

D

A

T

A

G

R

P

3

MISC

U41B

BGA479-SKT6-GPU7

2 OF 4

DATA GRP0DATA GRP1

D

A

T

A

G

R

P

2

D

A

T

A

G

R

P

3

MISC

U41B

BGA479-SKT6-GPU7

1 2R53 1KR2J-1-GPDYR53 1KR2J-1-GPDY12

R3542KR2F-3-GP

R3542KR2F-3-GP

1 2R350 27D4R2F-L1-GPR350 27D4R2F-L1-GP

1 2R60 1KR2J-1-GPDYR60 1KR2J-1-GPDY1 2R7 1KR2J-1-GPDYR7 1KR2J-1-GPDY1 2R58 1KR2J-1-GPDYR58 1KR2J-1-GPDY

1 2R349 54D9R2F-L1-GPR349 54D9R2F-L1-GP

1

2

C376SC1KP50V2KX-1GPDY C376SC1KP50V2KX-1GPDY

1 2R14 27D4R2F-L1-GPR14 27D4R2F-L1-GP1 2R13 54D9R2F-L1-GPR13 54D9R2F-L1-GP

1

2

R3571KR2F-3-GPR3571KR2F-3-GP

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_VID6

CPU_VID0CPU_VID1CPU_VID2CPU_VID3CPU_VID4CPU_VID5

CPU_GND3CPU_GND2

CPU_GND4

CPU_GND1

+VCC_CORE

+1.5V_RUN+1.5V_VCCA

+1.05V_VCCP

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

CPU_VID[6..0]

VCC_SENSE

VSS_SENSE

Title


Date: Sheet of


Roberts -3CPU-Power(3/3)

Custom


Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


layout note: "+1.5V_VCCA"as short as possible

VCC_SENSE and VSS_SENSE linesshould be of equal length.

Layout Note:Place as close as possibleto the CPU VCCA pin.

NCTFPIN

62.10040.221

62.10040.221

SSID = CPU

1

2

C

3

6

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C 36

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C10SC22U6D3V5MX-2GPC10SC22U6D3V5MX-2GP

1

2

C

3

6

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C 36

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

3

6

8

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

6

8

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

7

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

7

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

4

5

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

4

5

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2


1

2

C

4

4

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

4

4

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1 2R311 100R2F-L1-GP-UR311 100R2F-L1-GP-U

1

2

C

1

1

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C1

1

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

VSSAF2

VSSA4VSSA8VSSA11VSSA14VSSA16VSSA19VSSA23

VSSB6VSSB8VSSB11VSSB13VSSB16VSSB19VSSB21VSSB24VSSC5VSSC8VSSC11VSSC14VSSC16VSSC19VSSC2VSSC22VSSC25VSSD1VSSD4VSSD8VSSD11VSSD13VSSD16VSSD19VSSD23VSSD26VSSE3VSSE6VSSE8VSSE11VSSE14VSSE16VSSE19VSSE21VSSE24VSSF5VSSF8VSSF11VSSF13VSSF16VSSF19VSSF2VSSF22VSSF25VSSG4VSSG1VSSG23VSSG26VSSH3VSSH6VSSH21VSSH24VSSJ2VSSJ5VSSJ22VSSJ25VSSK1VSSK4VSSK23VSSK26VSSL3VSSL6VSSL21VSSL24VSSM2VSSM5VSSM22VSSM25VSSN1VSSN4VSSN23VSSN26VSSP3

VSS P6VSS P21VSS P24VSS R2VSS R5VSS R22VSS R25VSS T1VSS T4VSS T23VSS T26VSS U3VSS U6VSS U21VSS U24VSS V2VSS V5VSS V22VSS V25VSS W1VSS W4VSS W23VSS W26VSS Y3VSS Y6VSS Y21VSS Y24VSS AA2VSS AA5VSS AA8VSS AA11VSS AA14VSS AA16VSS AA19VSS AA22VSS AA25VSS AB1VSS AB4VSS AB8VSS AB11VSS AB13VSS AB16VSS AB19VSS AB23VSS AB26VSS AC3VSS AC6VSS AC8VSS AC11VSS AC14VSS AC16VSS AC19VSS AC21VSS AC24VSS AD2VSS AD5VSS AD8VSS AD11VSS AD13VSS AD16VSS AD19VSS AD22VSS AD25VSS AE1VSS AE4VSS AE8VSS AE11VSS AE14VSS AE16VSS AE19VSS AE23VSS AE26VSS A2VSS AF6VSS AF8VSS AF11VSS AF13VSS AF16VSS AF19VSS AF21VSS A25VSS AF25

4 OF 4U41D

BGA479-SKT6-GPU7

4 OF 4U41D

BGA479-SKT6-GPU7

1

2

C

9

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

9

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

3

6

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

6

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

3

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

3

5

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

5

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

3

3

8

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

3

8

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

1

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C1

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1 2R302 100R2F-L1-GP-UR302 100R2F-L1-GP-U

1

2

C

1

4

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

1

4

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

C

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

3

4

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

4

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1TP10TP10

1TP56TP56

1

2

C

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

C

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

3

7

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C 37

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

3

4

4

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

4

4

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C374SCD01U16V2KX-3GP


1

2

C

3

1

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C3

1

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C8SCD1U10V2KX-4GPC8SCD1U10V2KX-4GP

1

2

C

1

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

1

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

VCCA7VCCA9

VCCAC10

VCCA10VCCA12VCCA13VCCA15VCCA17VCCA18VCCA20VCCB7VCCB9VCCB10VCCB12VCCB14VCCB15VCCB17VCCB18VCCB20VCCC9VCCC10VCCC12VCCC13VCCC15VCCC17VCCC18VCCD9VCCD10VCCD12VCCD14VCCD15VCCD17VCCD18VCCE7VCCE9VCCE10VCCE12VCCE13VCCE15

VCCAA7VCCAA9VCCAA10VCCAA12VCCAA13VCCAA15VCCAA17VCCAA18VCCAA20VCCAB9

VCCAB12VCCAB14VCCAB15VCCAB17VCCAB18

VCCE17VCCE18VCCE20VCCF7VCCF9VCCF10VCCF12VCCF14VCCF15VCCF17VCCF18VCCF20

VCC AB20VCC AB7VCC AC7VCC AC9VCC AC12VCC AC13VCC AC15VCC AC17VCC AC18VCC AD7VCC AD9VCC AD10VCC AD12VCC AD14VCC AD15VCC AD17VCC AD18VCC AE9VCC AE10VCC AE12VCC AE13VCC AE15VCC AE17VCC AE18VCC AE20VCC AF9VCC AF10VCC AF12VCC AF14VCC AF15VCC AF17VCC AF18VCC AF20

VCCP G21

VCCP J6

VCCP J21

VCCP K6

VCCP K21

VCCP M6

VCCP M21

VCCP N6VCCP N21

VCCP R6VCCP R21

VCCP T6VCCP T21

VCCP V6

VCCP V21VCCP W21

VCCA B26VCCA C26

VID0 AD6

VID6 AE2

VID4 AE3

VID2 AE5

VID5 AF3

VID3 AF4

VID1 AF5

VSSSENSE AE7

VCCSENSE AF7

VCCAB10

3 OF 4U41C

BGA479-SKT6-GPU7

3 OF 4U41C

BGA479-SKT6-GPU7

1

2

C

2

9

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

2

9

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

T

C

1

7

S

T

2

2

0

U

2

D

5

V

B

M

-

L

G

P

DY T C1

7

S

T

2

2

0

U

2

D

5

V

B

M

-

L

G

P

DY

1

2

C

3

6

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

6

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

3

4

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

3

4

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

2

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C2

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

1

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

1

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

1

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C1

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

3

5

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C 35

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1TP20TP20

1

2


1

2

C

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

C

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

3

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C3

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1 2R3560R0603-PAD

R3560R0603-PAD

1

2

C

3

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C3

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1TP224TP224

1

2

C

4

3

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

4

3

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2


1

2

C

2

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C2

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1

2

C

3

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C3

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_D#[63..0]H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39H_D#40H_D#41H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47H_D#48H_D#49H_D#50H_D#51H_D#52H_D#53H_D#54H_D#55H_D#56H_D#57H_D#58H_D#59H_D#60H_D#61H_D#62H_D#63

H_AVREF

H_RCOMP

H_SWING

H_SWINGH_RCOMP

H_DINV#0

H_RS#1

H_DSTBN#0

H_REQ#2

H_DSTBP#0

H_REQ#4H_REQ#3

H_RS#0

H_DINV#3

H_DSTBN#3

H_DSTBP#3

H_REQ#1

H_DINV#2

H_DSTBN#2

H_DSTBP#2

H_REQ#0

H_DINV#1

H_RS#2

H_DSTBN#[3..0]

H_DSTBN#1

H_DSTBP#[3..0]

H_DSTBP#1

H_DINV#[3..0]

H_A#6

H_A#16

H_A#34

H_A#32

H_A#22

H_A#20

H_A#26

H_A#11

H_A#5

H_A#31

H_A#3

H_A#9

H_A#15

H_A#21

H_A#19

H_A#25

H_A#4

H_A#30H_A#29

H_A#8

H_A#14

H_A#18

H_A#24

H_A#28

H_A#7

H_A#13

H_A#17

H_A#12

H_A#35

H_A#33

H_A#23

H_A#27

H_A#10

H_A#[35..3]

H_REQ#[4..0]

H_RS#[2..0]

+1.05V_VCCP

+1.05V_VCCP

H_D#[63..0]

H_CPURST#H_CPUSLP#

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_REQ#[4..0]

H_RS#[2..0]

H_BNR#

H_BREQ#0

H_ADS#H_ADSTB#0H_ADSTB#1

H_DBSY#

H_DRDY#H_HIT#H_HITM#H_LOCK#

H_BPRI#

H_DEFER#

H_DPWR#

H_TRDY#

H_A#[35..3]

CLK_MCH_BCLKCLK_MCH_BCLK#

Title


Date: Sheet of


Roberts -3Cantiga-HOST(1/6)

Custom


Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


Place R51 near to the chip ( < 0.5")

H_RCOMP routing Trace width andSpacing use 10 / 20 mil

H_SWING routing Trace width andSpacing use 10 / 20 mil

H_SWING Resistors andCapacitors close MCH500 mil ( MAX )

SSID = MCH

1

2


1

2


1

2

R367100R2F-L1-GP-UR367100R2F-L1-GP-U

1 2R361 24D9R2F-L-GPR361 24D9R2F-L-GP

H_A#_10 P16H_A#_11 R16H_A#_12 N17H_A#_13 M13H_A#_14 E17H_A#_15 P17H_A#_16 F17H_A#_17 G20H_A#_18 B19H_A#_19 J16H_A#_20 E20H_A#_21 H16H_A#_22 J20H_A#_23 L17H_A#_24 A17H_A#_25 B17H_A#_26 L16H_A#_27 C21H_A#_28 J17H_A#_29 H20

H_A#_3 A14

H_A#_30 B18H_A#_31 K17

H_A#_4 C15H_A#_5 F16H_A#_6 H13H_A#_7 C18H_A#_8 M16H_A#_9 J13

H_ADS# H12H_ADSTB#_0 B16H_ADSTB#_1 G17

H_BNR# A9H_BPRI# F11

H_BREQ# G12

HPLL_CLK# AH6

H_CPURST#C12

HPLL_CLK AH7

H_D#_0F2

H_REQ#_2 F13H_REQ#_3 B13

H_D#_1G8

H_D#_10M9

H_D#_20L6

H_D#_30N10

H_D#_40AA8

H_D#_50AA2

H_D#_60AE11

H_D#_8D4H_D#_9H3

H_DBSY# B10

H_D#_11M11H_D#_12J1H_D#_13J2H_D#_14N12H_D#_15J6H_D#_16P2H_D#_17L2H_D#_18R2H_D#_19N9

H_D#_2F8

H_D#_21M5H_D#_22J3H_D#_23N2H_D#_24R1H_D#_25N5H_D#_26N6H_D#_27P13H_D#_28N8H_D#_29L7

H_D#_3E6

H_D#_31M3H_D#_32Y3H_D#_33AD14H_D#_34Y6H_D#_35Y10H_D#_36Y12H_D#_37Y14H_D#_38Y7H_D#_39W2

H_D#_4G2

H_D#_41Y9H_D#_42AA13H_D#_43AA9H_D#_44AA11H_D#_45AD11H_D#_46AD10H_D#_47AD13H_D#_48AE12H_D#_49AE9

H_D#_5H6

H_D#_51AD8H_D#_52AA3H_D#_53AD3H_D#_54AD7H_D#_55AE14H_D#_56AF3H_D#_57AC1H_D#_58AE3H_D#_59AC3

H_D#_6H2

H_D#_61AE8H_D#_62AG2H_D#_63AD6

H_D#_7F6

H_DEFER# E9

H_DINV#_0 J8H_DINV#_1 L3H_DINV#_2 Y13H_DINV#_3 Y1

H_DPWR# J11H_DRDY# F9

H_DSTBN#_0 L10H_DSTBN#_1 M7H_DSTBN#_2 AA5H_DSTBN#_3 AE6

H_DSTBP#_0 L9H_DSTBP#_1 M8H_DSTBP#_2 AA6H_DSTBP#_3 AE5

H_AVREFA11H_DVREFB11

H_TRDY# C9

H_HIT# H9H_HITM# E12

H_LOCK# H11

H_REQ#_0 B15H_REQ#_1 K13

H_REQ#_4 B14

H_A#_32 B20H_A#_33 F21H_A#_34 K21H_A#_35 L20

H_SWINGC5

H_CPUSLP#E11

H_RCOMPE3

H_RS#_0 B6H_RS#_1 F12H_RS#_2 C8

H

O

S

T

1 OF 10U52A

CANTIGA-GM-GP-U-NF

H

O

S

T

1 OF 10U52A

CANTIGA-GM-GP-U-NF

1

2

R368221R2F-2-GPR368221R2F-2-GP

1

2

C403SCD1U16V2KX-3GPDY C403SCD1U16V2KX-3GPDY

1

2


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DMI_TXP3

DMI_RXN3

DMI_TXN2DMI_TXN1DMI_TXN0

TSATN#

DMI_TXN3

DMI_RXP3DMI_RXP2DMI_RXP1DMI_RXP0

DMI_TXP2DMI_TXP1DMI_TXP0

DMI_RXN2DMI_RXN1DMI_RXN0

SM_RCOMP_VOHSM_RCOMP_VOL

CFG5CFG6CFG7CFG8CFG9CFG10CFG11CFG12CFG13

CFG16

CFG18

CFG20CFG19

MCH_CLVREF

SM_REXT

RSTIN#

CFG13

CFG18

M_RCOMPPM_RCOMPN

CFG7

CFG9

CFG8

CFG5

CFG16

CFG11

CFG10

CFG12

CFG19

CFG6

PM_EXTTS#1PM_EXTTS#0

TSATN#_KBC

TSATN#

SM_RCOMP_VOH

SM_RCOMP_VOL

CLK_MCH_3GPLL#CLK_MCH_3GPLL

CLK_MCH_DREFCLK#CLK_MCH_DREFCLK

MCH_SSCDREFCLK#MCH_SSCDREFCLK

CLKREQ#_B

CFG3CFG4

CFG14CFG15

CFG17

CFG20

+1.8V_SUS

+1.05V_VCCP

+3.3V_RUN

+3.3V_RUN+1.05V_VCCP

+1.8V_SUS

+1.8V_SUS

+V_DDR_MCH_REF

+3.3V_RUN

DMI_RXN0

DMI_TXN0DMI_TXN1

DMI_TXP1

DMI_TXN2DMI_TXN3

DMI_TXP0

DMI_TXP2DMI_TXP3

DMI_RXN1DMI_RXN2DMI_RXN3

DMI_RXP0

DMI_RXP2DMI_RXP3

DMI_RXP1

MCH_CLKSEL1MCH_CLKSEL2

MCH_CLKSEL0

M_CLK_DDR#2M_CLK_DDR#3

M_CLK_DDR0M_CLK_DDR1

M_CKE0M_CKE1M_CKE2M_CKE3

M_CLK_DDR2M_CLK_DDR3

M_CS1#M_CS2#M_CS3#

M_CS0#

M_CLK_DDR#0M_CLK_DDR#1

M_ODT0M_ODT1M_ODT2M_ODT3

CL_CLK0CL_DATA0

H_DPRSTP#PM_SYNC#

PLT_RST#

PM_PWROK

DPRSLPVRH_THRMTRIP#

MCH_ICH_SYNC#

PM_EXTTS#0PM_EXTTS#1

TSATN#_KBC

M_PWROKCL_RST#0

CLK_MCH_3GPLLCLK_MCH_3GPLL#

CLK_MCH_DREFCLKCLK_MCH_DREFCLK#MCH_SSCDREFCLKMCH_SSCDREFCLK#

CLKREQ#_B

Title


Date: Sheet of


Roberts -3Cantiga-DMI/CFG(2/6)

Custom


Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


FSB setting

MCH_CLVREF ~= 0.35V

SDVO/iHDMI/DP interface disabled

SDVO/iHDMI/DP interface enabled

DDPC_CTRLDATA

TLS cipher suite with confidentiality

CFG 16 FSB dynamic ODT disable

CFG Strap HighLowDMI X 2

CFG 9 PCIE GFX lane reversed

CFG 19DMI Lane Reserved

DMI X 4

Normal operation Reverse DMI lanes

ITPM enable

Only PCIE or SDVO is operational

ITPM disable

CFG 20SDVO concurrent with PCIE

PCIE and SDVO areoperatiing simultaneously via the PEG port

SDVO_CTRLDATA

CFG 5CFG 6

SDVO interface disable

CFG 7 TLS cipher suite with no confidentiality

FSB Dynamic ODT enable

CFG 10 PCIE loopback enable PCIE loopback disableCFG 12 ALLZ mode enable ALLZ mode disableCFG 13 XOR mode enable XOR mode disable

PCIE GFX lanenumbered in oder

SDVO interface enableL_DDC_DATA LFP disable LFP card present

SSID = MCH* is current setting

********

*****

-32009/07/27

1 2R105 2K21R2F-GPDYR105 2K21R2F-GPDY

1

2

C94SC100P50V2JN-3GP DYC94SC100P50V2JN-3GP DY


1

2

R1163K01R2F-3-GPR1163K01R2F-3-GP

1 2

R94

100R2J-2-GP

R94

100R2J-2-GP

1 TP271TP271

1

2



1

2


1TP84TP84

1

2



1 2

R14210KR2J-3-GP

DYR14210KR2J-3-GP

DY


1TP85TP85


1

2

R37780D6R2F-L-GP

R37780D6R2F-L-GP


1

2

R38080D6R2F-L-GP

R38080D6R2F-L-GP

1

2

R130499R2F-2-GPR130499R2F-2-GP

1 2R117 4K02R2F-GPDYR117 4K02R2F-GPDY1 2R121 4K02R2F-GPDYR121 4K02R2F-GPDY

1 2R131

10KR2J-3-GP

R131

10KR2J-3-GP

1

2

C145SC2D2U10V3KX-1GP



C

B

E

Q19MMBT3904WT1G-GPDY Q19MMBT3904WT1G-GPDY

SA_CK_0 AP24SA_CK_1 AT21SB_CK_0 AV24

SA_CK#_0 AR24SA_CK#_1 AR21SB_CK#_0 AU24

SA_CKE_0 BC28SA_CKE_1 AY28SB_CKE_0 AY36SB_CKE_1 BB36

SA_CS#_0 BA17SA_CS#_1 AY16SB_CS#_0 AV16SB_CS#_1 AR13

SM_DRAMRST# BC36

SA_ODT_0 BD17SA_ODT_1 AY17SB_ODT_0 BF15SB_ODT_1 AY13

SM_RCOMP BG22SM_RCOMP# BH21

CFG_18P29CFG_19R28

CFG_2P25

CFG_0T25CFG_1R25

CFG_20T28

CFG_3P20CFG_4P24CFG_5C25CFG_6N24CFG_7M24CFG_8E21CFG_9C23CFG_10C24CFG_11N21CFG_12P21CFG_13T21CFG_14R20CFG_15M20CFG_16L21CFG_17H21

PM_SYNC#R29

PM_EXT_TS#_0N33PM_EXT_TS#_1P32PWROKAT40RSTIN#AT11

DPLL_REF_CLK B38DPLL_REF_CLK# A38

DPLL_REF_SSCLK E41DPLL_REF_SSCLK# F41

DMI_RXN_0 AE41DMI_RXN_1 AE37DMI_RXN_2 AE47DMI_RXN_3 AH39

DMI_RXP_0 AE40DMI_RXP_1 AE38DMI_RXP_2 AE48DMI_RXP_3 AH40

DMI_TXN_0 AE35DMI_TXN_1 AE43DMI_TXN_2 AE46DMI_TXN_3 AH42

DMI_TXP_0 AD35DMI_TXP_1 AE44DMI_TXP_2 AF46DMI_TXP_3 AH43

RESERVED#AL34AL34

RESERVED#AN35AN35RESERVED#AK34AK34

RESERVED#AM35AM35

RESERVED#BG23BG23RESERVED#BF23BF23RESERVED#BH18BH18RESERVED#BF18BF18

PM_DPRSTP#B7

SB_CK_1 AU20

SB_CK#_1 AV20

RESERVED#AY21AY21

RESERVED#AH9AH9RESERVED#AH10AH10RESERVED#AH12AH12RESERVED#AH13AH13

RESERVED#M36M36RESERVED#N36N36RESERVED#R33R33RESERVED#T33T33

GFX_VID_0 B33GFX_VID_1 B32GFX_VID_2 G33GFX_VID_3 F33

GFX_VR_EN C34

SM_RCOMP_VOH BF28SM_RCOMP_VOL BH28

THERMTRIP#T20DPRSLPVRR32

RESERVED#K12K12

CL_CLK AH37CL_DATA AH36

CL_PWROK AN36CL_RST# AJ35CL_VREF AH34

NC#A47A47

NC#BG48BG48NC#BF48BF48NC#BD48BD48NC#BC48BC48NC#BH47BH47NC#BG47BG47NC#BE47BE47NC#BH46BH46NC#BF46BF46NC#BG45BG45NC#BH44BH44NC#BH43BH43NC#BH6BH6NC#BH5BH5NC#BG4BG4

SDVO_CTRLCLK G36SDVO_CTRLDATA E36

CLKREQ# K36

RESERVED#T24T24

ICH_SYNC# H36

TSATN# B12

PEG_CLK# E43PEG_CLK F43

NC#BH3BH3

GFX_VID_4 E33

RESERVED#B31B31

DDPC_CTRLCLK N28

NC#BF3BF3NC#BH2BH2NC#BG2BG2NC#BE2BE2NC#BG1BG1NC#BF1BF1NC#BD1BD1NC#BC1BC1NC#F1F1

SM_VREF AV42SM_PWROK AR36

SM_REXT BF17

RESERVED#M1M1

HDA_BCLK B28HDA_RST# B30

HDA_SDI B29HDA_SDO C29

HDA_SYNC A28

DDPC_CTRLDATA M28

RESERVED#B2B2

PM

M

I

S

C

NC

D

D

R

C

L

K

/

C

O

N

T

R

O

L

/

C

O

M

P

E

N

S

A

T

I

O

N

C

L

K

D

M

I

CFGRSVD

G

R

A

P

H

I

C

S

V

I

D

M

E

H

D

A

2 OF 10U52B

CANTIGA-GM-GP-U-NF

PM

M

I

S

C

NC

D

D

R

C

L

K

/

C

O

N

T

R

O

L

/

C

O

M

P

E

N

S

A

T

I

O

N

C

L

K

D

M

I

CFGRSVD

G

R

A

P

H

I

C

S

V

I

D

M

E

H

D

A

2 OF 10U52B

CANTIGA-GM-GP-U-NF

1

2


1TP86TP86

1TP87TP87

1

2


123

4RN20

SRN10KJ-5-GP

RN20

SRN10KJ-5-GP

1

2



1TP88TP88


1

2

R37056R2J-4-GPR37056R2J-4-GP


1

2

C

1

7

5

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

1

7

5

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1 2R374 499R2F-2-GPR374 499R2F-2-GP


1

2



1

2



55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQS#3

M_A_DQS#0

M_A_DQS#6

M_A_DQS#4

M_A_DQS#1M_A_DQS#2

M_A_DQS#5

M_A_DQS#7

M_A_A0

M_A_A6

M_A_A3

M_A_A5

M_A_A7

M_A_A1M_A_A2

M_A_A4

M_A_A10

M_A_A8

M_A_A13

M_A_A11

M_A_A9

M_A_A12

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_DM[7..0]M_A_DM0M_A_DM1M_A_DM2M_A_DM3M_A_DM4M_A_DM5M_A_DM6M_A_DM7

M_A_DQS[7..0]

M_A_DQS5

M_A_DQS7

M_A_DQS2M_A_DQS3M_A_DQS4

M_A_DQS0M_A_DQS1

M_A_DQS6

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_B_DQ[63..0]

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ[63..0]M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_B_DQS#[7..0]M_B_DQS#0M_B_DQS#1M_B_DQS#2M_B_DQS#3M_B_DQS#4M_B_DQS#5M_B_DQS#6M_B_DQS#7

M_B_DQS[7..0]M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_A12

M_B_A9

M_B_A11

M_B_A13

M_B_A8

M_B_A10

M_B_A[14..0]M_B_A0M_B_A1M_B_A2M_B_A3M_B_A4M_B_A5M_B_A6M_B_A7

M_B_DM[7..0]M_B_DM0M_B_DM1M_B_DM2M_B_DM3M_B_DM4M_B_DM5M_B_DM6M_B_DM7

M_A_A14M_B_A14

M_A_DQS#[7..0]

M_A_DQS[7..0]

M_A_A[14..0]

M_A_DM[7..0]

M_B_BS#0M_B_BS#1M_B_BS#2

M_B_CAS#M_B_RAS#

M_A_BS#0M_A_BS#1M_A_BS#2

M_A_CAS#

M_B_DQ[63..0]

M_A_RAS#

M_A_DQ[63..0]

M_B_DQS#[7..0]

M_B_DQS[7..0]

M_B_A[14..0]

M_B_DM[7..0]

M_A_WE#M_B_WE#

Title


Date: Sheet of


Roberts -3Cantiga-DDR(3/6)

Custom


Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


SSID = MCH

SB_DQ_0AK47SB_DQ_1AH46

SB_DQ_10BA48SB_DQ_11AY48SB_DQ_12AT47SB_DQ_13AR47SB_DQ_14BA47SB_DQ_15BC47SB_DQ_16BC46SB_DQ_17BC44SB_DQ_18BG43SB_DQ_19BF43

SB_DQ_2AP47

SB_DQ_20BE45SB_DQ_21BC41SB_DQ_22BF40SB_DQ_23BF41SB_DQ_24BG38SB_DQ_25BF38SB_DQ_26BH35SB_DQ_27BG35SB_DQ_28BH40SB_DQ_29BG39

SB_DQ_3AP46

SB_DQ_30BG34SB_DQ_31BH34SB_DQ_32BH14SB_DQ_33BG12SB_DQ_34BH11SB_DQ_35BG8SB_DQ_36BH12SB_DQ_37BF11SB_DQ_38BF8SB_DQ_39BG7

SB_DQ_4AJ46

SB_DQ_40BC5SB_DQ_41BC6SB_DQ_42AY3SB_DQ_43AY1SB_DQ_44BF6SB_DQ_45BF5SB_DQ_46BA1SB_DQ_47BD3SB_DQ_48AV2SB_DQ_49AU3

SB_DQ_5AJ48

SB_DQ_50AR3SB_DQ_51AN2SB_DQ_52AY2SB_DQ_53AV1SB_DQ_54AP3SB_DQ_55AR1SB_DQ_56AL1SB_DQ_57AL2SB_DQ_58AJ1SB_DQ_59AH1

SB_DQ_6AM48

SB_DQ_60AM2SB_DQ_61AM3SB_DQ_62AH3SB_DQ_63AJ3

SB_DQ_7AP48SB_DQ_8AU47SB_DQ_9AU46

SB_BS_0 BC16SB_BS_1 BB17SB_BS_2 BB33

SB_CAS# BG16

SB_DM_0 AM47SB_DM_1 AY47SB_DM_2 BD40SB_DM_3 BF35SB_DM_4 BG11SB_DM_5 BA3SB_DM_6 AP1SB_DM_7 AK2

SB_DQS_0 AL47SB_DQS_1 AV48SB_DQS_2 BG41SB_DQS_3 BG37SB_DQS_4 BH9SB_DQS_5 BB2SB_DQS_6 AU1SB_DQS_7 AN6

SB_DQS#_0 AL46SB_DQS#_1 AV47SB_DQS#_2 BH41SB_DQS#_3 BH37SB_DQS#_4 BG9SB_DQS#_5 BC2SB_DQS#_6 AT2SB_DQS#_7 AN5

SB_MA_0 AV17SB_MA_1 BA25

SB_MA_10 BB16SB_MA_11 AW33SB_MA_12 AY33SB_MA_13 BH15

SB_MA_2 BC25SB_MA_3 AU25SB_MA_4 AW25SB_MA_5 BB28SB_MA_6 AU28SB_MA_7 AW28SB_MA_8 AT33SB_MA_9 BD33

SB_MA_14 AU33

SB_RAS# AU17

SB_WE# BF14

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

5 OF 10U52E

CANTIGA-GM-GP-U-NF

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

5 OF 10U52E

CANTIGA-GM-GP-U-NF

SA_DQ_0AJ38SA_DQ_1AJ41

SA_DQ_10AU40SA_DQ_11AT38SA_DQ_12AN41SA_DQ_13AN39SA_DQ_14AU44SA_DQ_15AU42SA_DQ_16AV39SA_DQ_17AY44SA_DQ_18BA40SA_DQ_19BD43

SA_DQ_2AN38

SA_DQ_20AV41SA_DQ_21AY43SA_DQ_22BB41SA_DQ_23BC40SA_DQ_24AY37SA_DQ_25BD38SA_DQ_26AV37SA_DQ_27AT36SA_DQ_28AY38SA_DQ_29BB38

SA_DQ_3AM38

SA_DQ_30AV36SA_DQ_31AW36SA_DQ_32BD13SA_DQ_33AU11SA_DQ_34BC11SA_DQ_35BA12SA_DQ_36AU13SA_DQ_37AV13SA_DQ_38BD12SA_DQ_39BC12

SA_DQ_4AJ36

SA_DQ_40BB9SA_DQ_41BA9SA_DQ_42AU10SA_DQ_43AV9SA_DQ_44BA11SA_DQ_45BD9SA_DQ_46AY8SA_DQ_47BA6SA_DQ_48AV5SA_DQ_49AV7

SA_DQ_5AJ40

SA_DQ_50AT9SA_DQ_51AN8SA_DQ_52AU5SA_DQ_53AU6SA_DQ_54AT5SA_DQ_55AN10SA_DQ_56AM11SA_DQ_57AM5SA_DQ_58AJ9SA_DQ_59AJ8

SA_DQ_6AM44

SA_DQ_60AN12SA_DQ_61AM13SA_DQ_62AJ11SA_DQ_63AJ12

SA_DQ_7AM42SA_DQ_8AN43SA_DQ_9AN44

SA_BS_0 BD21SA_BS_1 BG18SA_BS_2 AT25

SA_CAS# BD20

SA_DM_0 AM37SA_DM_1 AT41SA_DM_2 AY41SA_DM_3 AU39SA_DM_4 BB12SA_DM_5 AY6SA_DM_6 AT7

SA_DQS_0 AJ44SA_DQS_1 AT44SA_DQS_2 BA43SA_DQS_3 BC37SA_DQS_4 AW12SA_DQS_5 BC8SA_DQS_6 AU8SA_DQS_7 AM7

SA_DM_7 AJ5

SA_DQS#_0 AJ43SA_DQS#_1 AT43SA_DQS#_2 BA44SA_DQS#_3 BD37SA_DQS#_4 AY12SA_DQS#_5 BD8SA_DQS#_6 AU9SA_DQS#_7 AM8

SA_MA_0 BA21SA_MA_1 BC24

SA_MA_10 BC21SA_MA_11 BG26SA_MA_12 BH26SA_MA_13 BH17

SA_MA_2 BG24SA_MA_3 BH24SA_MA_4 BG25SA_MA_5 BA24SA_MA_6 BD24SA_MA_7 BG27SA_MA_8 BF25SA_MA_9 AW24

SA_RAS# BB20

SA_WE# AY20

SA_MA_14 AY25

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

A

4 OF 10U52D

CANTIGA-GM-GP-U-NF

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

A

4 OF 10U52D

CANTIGA-GM-GP-U-NF

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_GMCH_35

SM_LF7_GMCHSM_LF6_GMCH

SM_LF3_GMCHSM_LF2_GMCHSM_LF1_GMCH

SM_LF5_GMCHSM_LF4_GMCH

VCC_AXG_SENSEVSS_AXG_SENSE

+1.05V_VCCP+1.8V_SUS

+1.05V_VCCP

+1.8V_SUS

+1.05V_VCCP

+1.05V_VCCP

Title


Date: Sheet of


Roberts -3Cantiga-Power(4/6)

Custom

11 59Monday, July 27, 2009

Title


Date: Sheet of



Custom

11 59Monday, July 27, 2009

Title


Date: Sheet of



Custom

11 59Monday, July 27, 2009

FOR VCC SM

Place on the Edge

Place CAP whereLVDS and DDR2 taps

FOR VCC CORE

Coupling CAP 370 mils from the Edge

Place on the Edge

Coupling CAP

Coupling CAP

+1.05V_VCCP 50mAVCC_AXFVCC_HDA+1.5V_RUN 50mA

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP+1.05V_VCCP+1.05V_VCCP

157.2mAVCCD_HPLL

VCCA_SM_CK 26mA

139.2mAVCCA_MPLLVCCA_HPLL 24mA

720mA+1.05V_VCCP+1.05V_VCCP

VCCA_SM

+1.05V_VCCP50mAVCCA_PEG_PLL

+1.8V_SUS+1.8V_SUS 124mA

Supply Signal Group

VCC_AXG2898.52mAVCC+1.05V_VCCPImax

1782mAVCC_PEG852mAVTT8700mA

3000mAVCC_SM

456mAVCC_DMI

VCC_SM_CK

+1.05V_VCCP+1.05V_VCCP

+1.5V_RUN VCCD_TVDAC 35mA

+3.3V_RUN VCCA_PEG_BG 414uA

+1.05V_VCCP

+3.3V_RUN VCC_HV 105.3mA

321.35mA

VCCD_LVDS

VCCD_PEG_PLL

+1.8V_SUS 60.31mA

8700mA

2898.52mA

3000mA

SSID = MCH

SB

1

2

C

8

0

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

8

0

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

8

1

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

C

8

1

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

1

2

T

C

1

9

S

T

2

2

0

U

2

D

5

V

B

M

-

2

G

P

T

C

1

9

S

T

2

2

0

U

2

D

5

V

B

M

-

2

G

P

1

2

T

C

2

1

S

T

2

2

0

U

2

D

5

V

B

M

-

2

G

P

T

C

2

1

S

T

2

2

0

U

2

D

5

V

B

M

-

2

G

P

2

1

C

1

8

2

S

C

D

4

7

U

6

D

3

V

2

K

X

-

G

P

2

1

C

1

8

2

S

C

D

4

7

U

6

D

3

V

2

K

X

-

G

P

1

2

C

1

1

3

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

C

1

1

3

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

1TP83TP83

1

2

C

1

5

6

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

1

5

6

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

1

4

2

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

1

4

2

S

C

1

U

1

0

V

3

K

X

-

3

G

P

1

2

C

4

2

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C 42

6

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY1

2

C

3

8

3

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

C

3

8

3

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

1

2

C

1

6

6

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

1

6

6

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

VCC_NCTF AM32

VCC_NCTF AC30

VCC_NCTF AJ29

VCC_NCTF AK25

VCC_NCTF AA32VCC_NCTF Y32VCC_NCTF W32VCC_NCTF U32VCC_NCTF AM30VCC_NCTF AL30VCC_NCTF AK30

VCC_NCTF AG30VCC_NCTF AF30VCC_NCTF AE30

VCC_NCTF AL32

VCC_NCTF W30VCC_NCTF V30

VCC_NCTF AK32

VCC_NCTF AH29VCC_NCTF AG29VCC_NCTF AE29

VCC_NCTF AL28VCC_NCTF AK28VCC_NCTF AL26VCC_NCTF AK26

VCC_NCTF AJ32

VCC_NCTF AK24

VCC_NCTF AH32VCC_NCTF AG32VCC_NCTF AE32VCC_NCTF AC32

VCC_NCTF AC29VCC_NCTF AA29VCC_NCTF Y29VCC_NCTF W29VCC_NCTF V29

VCC_NCTF U30VCC_NCTF AL29VCC_NCTF AK29

VCC_NCTF AH30

VCC_NCTF AB30VCC_NCTF AA30VCC_NCTF Y30

VCCAG34VCCAC34VCCAB34VCCAA34VCCY34VCCV34VCCU34VCCAM33VCCAK33VCCAJ33VCCAG33VCCAF33

VCCAE33VCCAC33VCCAA33VCCY33VCCW33VCCV33VCCU33VCCAH28VCCAF28VCCAC28VCCAA28VCCAJ26VCCAG26VCCAE26VCCAC26VCCAH25VCCAG25VCCAF25VCCAG24VCCAJ23VCCAH23VCCAF23

VCCT32

VCC_NCTF AK23

P

O

W

E

R

V

C

C

N

C

T

F

V

C

C

C

O

R

E

6 OF 10U52F

CANTIGA-GM-GP-U-NF

P

O

W

E

R

V

C

C

N

C

T

F

V

C

C

C

O

R

E

6 OF 10U52F

CANTIGA-GM-GP-U-NF

1

2

C

1

1

0

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

1

1

0

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

VCC_SMAY32

VCC_SMBF31

VCC_SMAW29

VCC_SMBD32VCC_SMBC32VCC_SMBB32VCC_SMBA32

VCC_SMAW32VCC_SMAV32VCC_SMAU32VCC_SMAT32VCC_SMAR32VCC_SMAP32VCC_SMAN32VCC_SMBH31VCC_SMBG31

VCC_SMAN33

VCC_SMBG30VCC_SMBH29VCC_SMBG29VCC_SMBF29VCC_SMBD29VCC_SMBC29VCC_SMBB29VCC_SMBA29VCC_SMAY29

VCC_SMBH32

VCC_SMAV29VCC_SMAU29VCC_SMAT29VCC_SMAR29

VCC_AXG_NCTF V23VCC_AXG_NCTF AM21VCC_AXG_NCTF AL21VCC_AXG_NCTF AK21VCC_AXG_NCTF W21VCC_AXG_NCTF V21VCC_AXG_NCTF U21VCC_AXG_NCTF AM20VCC_AXG_NCTF AK20VCC_AXG_NCTF W20

VCC_AXG_NCTF V28

VCC_AXG_NCTF U20VCC_AXG_NCTF AM19VCC_AXG_NCTF AL19VCC_AXG_NCTF AK19VCC_AXG_NCTF AJ19VCC_AXG_NCTF AH19VCC_AXG_NCTF AG19VCC_AXG_NCTF AF19VCC_AXG_NCTF AE19VCC_AXG_NCTF AB19

VCC_AXG_NCTF W26

VCC_AXG_NCTF AA19VCC_AXG_NCTF Y19VCC_AXG_NCTF W19VCC_AXG_NCTF V19VCC_AXG_NCTF U19VCC_AXG_NCTF AM17VCC_AXG_NCTF AK17VCC_AXG_NCTF AH17VCC_AXG_NCTF AG17VCC_AXG_NCTF AF17

VCC_AXG_NCTF V26

VCC_AXG_NCTF AE17VCC_AXG_NCTF AC17VCC_AXG_NCTF AB17VCC_AXG_NCTF Y17VCC_AXG_NCTF W17VCC_AXG_NCTF V17VCC_AXG_NCTF AM16VCC_AXG_NCTF AL16VCC_AXG_NCTF AK16VCC_AXG_NCTF AJ16

VCC_AXG_NCTF W25

VCC_AXG_NCTF AH16VCC_AXG_NCTF AG16VCC_AXG_NCTF AF16VCC_AXG_NCTF AE16VCC_AXG_NCTF AC16VCC_AXG_NCTF AB16VCC_AXG_NCTF AA16

VCC_AXG_NCTF V25VCC_AXG_NCTF W24VCC_AXG_NCTF V24VCC_AXG_NCTF W23

VCC_SMAP29

VCC_SMBG32VCC_SMBF32

VCC_AXG_NCTF W28VCC_SMAP33

VCC_AXGY26VCC_AXGAE25VCC_AXGAB25VCC_AXGAA25VCC_AXGAE24VCC_AXGAC24VCC_AXGAA24VCC_AXGY24VCC_AXGAE23VCC_AXGAC23VCC_AXGAB23VCC_AXGAA23VCC_AXGAJ21VCC_AXGAG21VCC_AXGAE21VCC_AXGAC21VCC_AXGAA21VCC_AXGY21VCC_AXGAH20VCC_AXGAF20VCC_AXGAE20VCC_AXGAC20VCC_AXGAB20VCC_AXGAA20VCC_AXGT17

VCC_AXGAM15VCC_AXGAL15

VCC_AXGAJ15VCC_AXGAH15

VCC_AXGAF15VCC_AXGAB15

VCC_SM_LF AV44VCC_SM_LF BA37VCC_SM_LF AM40VCC_SM_LF AV21VCC_SM_LF AY5VCC_SM_LF AM10VCC_SM_LF BB13

VCC_AXGT16

VCC_AXGAG15

VCC_AXGAA15VCC_AXGY15VCC_AXGV15VCC_AXGU15VCC_AXGAN14VCC_AXGAM14VCC_AXGU14VCC_AXGT14

VCC_AXG_SENSEAJ14VSS_AXG_SENSEAH14

VCC_AXG_NCTF Y16VCC_AXG_NCTF W16VCC_AXG_NCTF V16VCC_AXG_NCTF U16

VCC_SM/NCBA36VCC_SM/NCBB24VCC_SM/NCBD16VCC_SM/NCBB21VCC_SM/NCAW16VCC_SM/NCAW13VCC_SM/NCAT13

VCC_AXGAE15

P

O

W

E

R

V

C

C

S

M

V

C

C

G

F

X

V

C

C

G

F

X

N

C

T

F

V

C

C

S

M

L

F

7 OF 10U52G

CANTIGA-GM-GP-U-NF

P

O

W

E

R

V

C

C

S

M

V

C

C

G

F

X

V

C

C

G

F

X

N

C

T

F

V

C

C

S

M

L

F

7 OF 10U52G

CANTIGA-GM-GP-U-NF

1

2

C

9

8

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

9

8

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

4

3

1

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

4

3

1

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

1

8

6

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

1

8

6

S

C

1

U

1

0

V

3

K

X

-

3

G

P

1

2

C

1

7

8

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

1

7

8

S

C

1

U

1

0

V

3

K

X

-

3

G

P

1

2

C

1

0

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

1

0

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

9

1

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

C

9

1

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

1

2

C

9

2

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

9

2

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

1

1

1

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

C

1

1

1

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

1TP82TP82

1

2

C

1

7

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

1

7

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

2

1

C

1

6

1

S

C

D

4

7

U

6

D

3

V

2

K

X

-

G

P

2

1

C

1

6

1

S

C

D

4

7

U

6

D

3

V

2

K

X

-

G

P

1

2

C

8

4

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

8

4

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

1

6

4

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

1

6

4

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1 2R1250R0402-PAD

R1250R0402-PAD

1

2

C

4

3

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

4

3

5

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

9

9

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

9

9

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

1

7

3

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

1

7

3

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

1

3

4

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

C

1

3

4

S

C

D

2

2

U

1

0

V

2

K

X

-

1

G

P

1

2

C

3

9

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C 39

0

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1D8V_TXLVDS_S3

1D5VRUN_QDAC

1D8V_SUS_DLVDS

1D5VRUN_TVDAC

1D05V_RUN_HPLL

M_VCCA_DPLLA

M_VCCA_DPLLB

M_VCCA_MPLL

M_VCCA_HPLL

M_VCCA_DAC_BG

1D05V_SM_CK

1D5VRUN_QDAC

1D5VRUN_TVDAC

VCCA_PEG_BG

1D05V_RUN_PEGPLL

3D3V_CRTDAC_S0

M_VCCA_HPLL

M_VCCA_MPLL

M_VCCA_DPLLA

M_VCCA_DPLLB

1D05V_VCC_AXF

VTTLF1VTTLF2VTTLF3

VCC_HDA

1D8V_TXLVDS

1D05V_RUN_PEGPLL

1D05V_RUN_PEGPLL

+1.8V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP+3.3V_RUN +3.3V_VCC_HV

+3.3V_TV_DAC+3.3V_CRT_LDO

+1.8V_SUS

+1.05V_VCCP

+1.8V_SUS

+1.8V_SUS

+1.05V_VCCP

+3.3V_CRT_LDO

+3.3V_CRT_LDO

+1.05V_VCCP

+1.5V_RUN

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+3.3V_CRT_LDO

+1.5V_RUN

+1.05V_VCCP

+1.05V_VCCP+5V_RUN

+3.3V_VCC_HV

Title


Date: Sheet of


Roberts -3Cantiga-Power/Filter(5/6)

Custom

12 59Monday, July 27, 2009

Title


Date: Sheet of



Custom

12 59Monday, July 27, 2009

Title


Date: Sheet of



Custom

12 59Monday, July 27, 2009

220ohm 100MHz

120ohm 100MHz

120ohm 100MHz

180ohm 100MHz

Reserved for TV ripple

8

5

2

m

A

1

7

8

2

m

A

4

5

6

m

A

414uA

720mA26mA

24mA139.2mA

157.2mA

50mA

50mA3

2

1

.

3

5

m

A

50mA

35mA

60.31mA

1

2

4

m

A

1

0

5

.

3

m

A

73mA

5mA

64.8mA

13.2mA

79mA

2mA

118.8mA

SSID = MCH

Main source:74.09091.H3F2nd source:74.09198.07F

A00.08/0903

SB

1

2

C

4

2

7

S

C

D

0

1

U

1

6

V

2

K

X

-

3

G

P

C

4

2

7

S

C

D

0

1

U

1

6

V

2

K

X

-

3

G

P

1

2


1

2

C

1

5

8

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

1

5

8

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1

2

C

1

2

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY C 12

7

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

DY

1 2L12

FCM1608KF-1-GP

L12

FCM1608KF-1-GP

1 2R970R0805-PAD

R970R0805-PAD

1

2

C

3

8

5

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

3

8

5

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1 2R4020R0402-PAD

R4020R0

Documents

Dell Inspiron 1545 - Wistron Dr1 Roberts Uma - 48.4aq01.031 08212-3