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va

V8

dc

V8

dc

V8

dc

V8

dc

va

V8

dc

V8

dc

V4

dc

va

V2

dc

V2

dc

(a) (b) (c)

Figure 1. Multilevel inverters: (a) NPC; (b) 1-1-1-1; (c) 1-1-2

This work was supported by Conselho Nacional de DesenvolvimentoCientífico e Tecnológico - CNPq", "Coordenação de Aperfeiçoamentode Pessoal de Ensino Superior - CAPES" and "Fundação de Amparo àPesquisa do Estado do Rio Grande do Sul - FAPERGS".

Power Losses Analysis and Cooling System Design of Three Topologies of Multilevel

InvertersZambra, D.A.B.*, Rech, C.**, Gonçalves, F.A.S.***, Pinheiro, J.R.*

* Federal University of Santa Maria/Power Electronics and Control Research Group, Santa Maria, Brazil ** Santa Catarina State University /Department of Electrical Engineering, Joinville, Brazil *** São Paulo State University/Department of Electrical Engineering, Ilha Solteira, Brazil

Abstract—This paper presents the comparison of three topologies of multilevel inverters applied to drive an induction motor of 500 kVA/4.16 kV. The multilevel inverters analyzed are: a neutral point clamped inverter, a symmetrical cascaded multilevel inverter and a hybrid asymmetrical cascaded multilevel inverter. The performance indexes used in the comparison are total harmonic distortion, first order distortion factor, semiconductors power losses distribution and heat-sink volume. The comparison is developed with the purpose of finding the efficiency and the heat-sink volume where the three systems present the same output filter.

I. INTRODUCTION

The industry has available three topologies of multilevel inverters to use in drive systems. The neutral point clamped multilevel inverter, the flying capacitor multilevel inverter and the symmetrical cascaded multilevel inverter. However, other topologies are presented in the literature and present interesting characteristics.

The existences of different systems to use in same application conduct the researchers analyze what system is the most indicate. Some comparative studies regarding multilevel inverter topologies had already been considered in literature, as the comparison of the power losses between diode-clamped multilevel inverters of three and four levels presented [1], and involving an inverter with H-bridge cells and a two-level inverter shown in [2]. In addition, there are comparisons among diode-clamped, flying-capacitor and cascaded multilevel inverters, [3], between hybrid multilevel inverters with the same number of cells connected in series, [4], between symmetrical and hybrid asymmetrical multilevel inverters with the same number of levels in output voltage, [5] and among three topologies of multilevel inverters presented by [6]. The topics study in these comparisons was: total harmonic distortion, first order distortion factor and semiconductors power losses.

However, literature still lacks a comparison in terms of the heat-sink volume. Then, the main subject of this paper is compare the symmetrical and the hybrid asymmetrical cascade multilevel inverters with the same number of

levels in the output voltage and the neutral point clamped inverter, which is the most commonly used multilevel inverter. It is given emphasis in the power losses analysis and in the cooling system design to determine the heat-sink design volume.

II. DRIVE SYSTEMS

The multilevel inverter shown hereinafter are designed to supply an induction motor with line-voltage of 4160V, phase-current 68.4A, apparent power of 500kVA, frequency 60 Hz and power factor of 0.85.

A. Neutral Point Clamped Inverter One phase of a neutral point clamped inverter can be

seen in Fig.1 (a). The other phases of this inverter use the same DC link. The maximum voltage in the semiconductors is 3400V. Therefore, the devices used in this topology are the modules of IGBTs/diodes FZ200R65KF1, [7].

B. Inverter Nine-level Symmetrical Inverter One phase of a nine-level symmetrical inverter can be

seen in Fig.1 (b). This inverter is known as 1-1-1-1, because it presents four H-bridge series-connected cells with the same DC input voltage source. To generate a phase-voltage with peak value of 3400V, the DC sources must be equal to 850V. The device used to implement the H-bridge cells is the module BSM200GB170DLC, [8].

C. Inverter Nine-levelHybrid Asymmetrical Inverter One phase of a nine-level hybrid asymmetrical inverter

can be seen in Fig.1(c). This configuration is known as

978-1-4244-1668-4/08/$25.00 ©2008 IEEE

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Time [s]0 0.004 0.008 0.012 0.016

-1-0.75

-0.50

-0.25

00.25

0.50

0.75

1

Am

plitu

de[p

.u.]

(a)

Time [s]0 0.004 0.008 0.012 0.016

-1-0.75

-0.50

-0.25

00.25

0.50

0.75

1

Am

plitu

de[p

.u.]

(b)

(c)

Figure 2. Modulation techniques: (a) Phase disposition; (b) Phase-shift; (c) Hybrid

1-1-2 and receives this name because the amplitude of the normalized voltage that supplies the cell 3 is twice the amplitude of cells 1 and 2. The DC voltage sources of cells 1 and 2 are equal to 850 V, while the DC voltage source of cell 3 is 1700V. The devices used to implement the inverter are the GTOs DG408BP45, [9], and the diodes DSF8045SK, [10], for the highest power cell (cell 3) and for the lower power cells (cells 1 and 2) the module of IGBTs/diodes BSM200GB170DLC, [8].

III. MODULATION TECHNIQUE

The modulation techniques used with every converter are presented in this section.

A. Phase Disposition The phase disposition PWM modulation technique was

used with the NPC inverter. The reference signal and the two carriers can be verified in Fig.2 (a). In this strategy, the most significant harmonic appear around the carrier frequency. However, this component does not appear in line voltage. This technique guarantees only odd harmonics for odd values of mf, [11].

B. Phase-Shift The phase-shift PWM modulation technique was used

[11], [12]. To generate a phase-voltage with m levels, this strategy uses (m–1) carriers with the same amplitude, but with 360/(m–1) degrees phase-shift among themselves. For a m-level converter, the most significant harmonics will be located in lateral bands around (m–1)fp, where fp is the carrier frequency. For even values of the modulation frequency index (mf), the waveforms synthesized present quarter-wave symmetry, resulting only even harmonics [12]. Therefore, for a nine-level inverter, this strategy uses eight carriers with 45º phase-shift among themselves, as can be seen in Fig.2 (b).

C. Hybrid The hybrid multilevel modulation technique is used to

guarantee that some cells operate in low-frequency and

other in high-frequency. This strategy associates the stepped voltage waveform synthesis in higher power cells with high-frequency PWM modulation for the lowest power. The diagram that describes this modulation strategy can be verified in Fig.2 (c), where V3, V2 and V1are the normalized amplitude of DC sources that supply each cell, 3 and 2 represents the comparison levels of cell 3 and 2, r3(t), r2(t) and r1(t), are the reference signals, v3(t), v2(t) and v1(t) are the output voltage of each cell and vout(t) is the output phase-to-neutral voltage.

The comparison levels employed in the comparison are the constant levels, 3=2 and 2=1. The comparison analysis presented in the paper was developed for amplitude modulation index (ma) equal to 1.

IV. PERFORMANCE INDEXES

The performance indexes used in the comparative analysis are total harmonic distortion (THD), first order distortion factor (DF1) of the output voltages, semiconductors power losses and heat-sink volume.

A. Total Harmonic Distortion The total harmonic distortion of a signal is the ratio of

the sum of the powers of all harmonic frequencies above the fundamental frequency to the power of the fundamental frequency (1).

2

21

100% h

h

THD VV

∞

=

= (1)

B. First Order Distortion Factor In induction motors applications, the leakage

inductances provide first order attenuation [11]. Therefore, the DF1 represents the first order attenuation of the harmonics in the output voltage of the inverter. The DF1 is given by (2):

2

21

1001% h

h

VDF

V h

∞

=

= (2)

C. Semiconductors Power Losses Semiconductor devices employed in each configuration

were defined from their characteristics and they were presented in section II.

The semiconductors power losses can be estimated from the curves (vsat( ) x Il( )) and (E( ) x Il( )), presented in the datasheet of each device, where: vsat is the on-state saturation voltage (vce( ) for the IGBT, vF( ) for the diode and vTM( ) for the GTO); E( ) represent the energy losses in one commutation (Eon( ) if it is a turn-on commutation, Eoff( ) if it is a turn-off commutation and Erec( ) if it is a diode reverse recovery process).

These curves are used in a Matlab script developed to determinate the power losses. This software uses the mathematical modes that better represent the functions vce(il(θ)), vF(il(θ)), Eon(ilθ)), Eoff(il(θ)) and Erec(il(θ)) for each semiconductor device. The mathematical models are found using the points extracted of datasheets of each semiconductor and using one tool of Matlab identified as cftool (curve fitting tool).

The mathematical models obtained for module BSM200GB170DLC are given by (3)-(7), for the GTO DG408BP45 and diode DSF8045SK are given by (8)-(11) and for the module FZ200R65KF1 are given by (12)-(16).

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(a) (b)

(c) (d)

Figure 3. Thermal equivalent circuit: (a) traditional; (b) 1 switch or 1 diode; (c) module with 1 switch and 1 diode; (d) module with 2 switch

and 2 diode

0.470.27 ( ) 0.025BSMce lv I θ= ⋅ + (3)

0.380.29 ( ) 0.057BSMF lv I θ= ⋅ − (4)

( )(0.004 ( )) (0.002 ( )) 398.93 95.77 10l l

BSM

I IonE e eθ θ⋅ ⋅ −= ⋅ − ⋅ ⋅ (5)

( )(0.002 ( )) ( 0.003 ( )) 363.57 63.78 10l l

BSM

I IoffE e eθ θ⋅ − ⋅ −= ⋅ − ⋅ ⋅ (6)

( )(0.0002 ( )) ( 0.011 ( )) 355.87 63.31 10l l

BSM

I IrecE e eθ θ⋅ − ⋅ −= ⋅ − ⋅ ⋅ (7)

20.26 ( ) 2.32 ( ) 1.47DGTM l lv I Iθ θ= − ⋅ + ⋅ + (8)

6 22.79 10 ( ) 0.005 ( ) 1.19DSFF l lv I Iθ θ−= − ⋅ ⋅ + ⋅ + (9)

( )5 2 34 10 ( ) 1.43 ( ) 220 10DGon l lE I Iθ θ− −= ⋅ ⋅ + ⋅ + ⋅ (10)

( )4 2 38 10 ( ) 4 ( ) 189.1 10DGoff l lE I Iθ θ− −= − ⋅ ⋅ + ⋅ − ⋅ (11)

(0.002 ( )) ( 0.015 ( ))3.78 2.70l l

FZ

I Icev e eθ θ⋅ − ⋅= ⋅ − ⋅ (12)

(0.0016 ( )) ( 0.015 ( ))2.9 2.35l l

FZ

I IFv e eθ θ⋅ − ⋅= ⋅ − ⋅ (13)

( )(0.004 ( )) ( 0.004 ( )) 31058 1011 10l l

FZ

I IonE e eθ θ⋅ − ⋅ −= ⋅ − ⋅ ⋅ (14)

( )(0.002 ( )) ( 0.005 ( )) 31051 1097 10l l

FZ

I IoffE e eθ θ⋅ − ⋅ −= ⋅ − ⋅ ⋅ (15)

( )(0.004 ( )) 3211 10l

FZ

IrecE e θ⋅ −= ⋅ ⋅ (16)

Based on the models for each device, the conduction and switching power losses are calculated for each semiconductor of the inverter. The sum of all results is computed to obtain the total power losses.

The conduction power losses are those that occur while the semiconductor device is conducting current. The conduction power losses are given by (17) for the main switch (IGBT or GTO) or given by (18) for the diode.

( ) ( ) ( )2.

_0

12.SWcond sat l cmd swxP v i v d

π

θ θ θ θπ

= ⋅ ⋅ (17)

( ) ( ) ( )2.

_0

12.Dcond F l cmd swxP v i v d

π

θ θ θ θπ

= ⋅ ⋅ (18)

m( ) I ( )l a áxi m senθ θ φ= ⋅ ⋅ − (19) Where il(θ) is the load current (19), ma is the

modulation amplitude index, φ is the load displacement angle and vcmd_swx(θ) is the command signal of the switch SWx.

The total conduction losses are obtained by:

TOTAL SW Dcond cond condP P P= + (20) The switching losses are obtained by identifying every

turn-on and turn-off instants during one reference period. Therefore, the turn-on, turn-off and reverse recovery losses are given by (21), (22) and (23), respectively.

( )( )1on on lP E i

Tθ= (21)

( )( )1off off lP E i

Tθ= (22)

( )( )1rec rec lP E i

Tθ= (23)

Total switching losses are the sum of turn-on, turn-off and reverse recovery losses of all semiconductor devices:

TOTALcomut on off recP P P P= + + (24) Total losses are the sum of all conduction and switching

power losses:

TOTAL TOTALTOTAL comut comutP P P= + (25)

D. Heat-sink Design Semiconductor power losses are dissipated in the form

of heat. The reliability and the life expectancy of any semiconductor device are straight related to the maximum device junction temperature experienced, [13], therefore, the accurately thermal design is essential.

The one-dimensional model is given in terms of the thermal resistance which is defined as a ratio of temperature to power dissipation, (26). Where: Pd is the average power dissipation; THSsw is temperature of heat-sink; and Ta is ambient temperature.

HSsw aHSsw

dsw

T TR

Pθ−

= (26)

The heat-sink temperature (THSsw) is given by:

max ( )HSsw j dsw j c c sT T P R Rθ θ− −= − ⋅ + (27) The advantage of the one-dimensional model is the

simplicity. This model suppose that all heat is transferred for the ambient by the heat-sink finned, it consider that the temperature is constant in all surface of the heat-sink. Then, the application of the one-dimensional model is subordinate at follow restrictions:

• Junction temperature is consider constant (steady state);

• Only one power-dissipation device, in center of the heat-sink;

The traditional thermal equivalent circuit is presented in Fig.3 (a), where: R j-c is the thermal resistance between the junction and case, R c-s is the thermal resistance between the case and heat-sink, R s-a is the thermal resistance between the heat-sink and the ambient and R c-a is the thermal resistance between the case and the ambient. This resistance (R c-a) is consider large compared with the other model components, and then it can be consider with an open circuit.

Fig.3 (b) shows the model of one switch or diode, this model was used to define the heat-sink resistance of the devices DG408BP45 and DSF8045SK. Fig.3 (c) shows the circuit that represent a module with one switch and one diode and it is used to obtain the heat-sink resistance of the module FZ200R65KF1. Fig.3 (d) shows the circuit that represents a module with two switches and two diodes

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and it is used to obtain the heat-sink resistance of the module BSM200GB170DLC. The two last models present only one resistance between the case and heat-sink because the devices are package together. The thermal resistances of the semiconductors used in the heat-sink design were extracted of the datasheet of each device or module and are presented in Table 1.

To continue the heat-sink design there is the requirement of define the heat-sink profile. The profile chosen is the HS21577, made by HS Dissipadores, [14]. This profile can be seen in Fig.4 (a) and (b), respectively three and one-dimensional view. The use of finned-type heat-sinks is a good option because it increases the sink surface area and makes decrease the thermal resistance. Fig.4 (c) shows the relation of the thermal resistance with the length of heat-sink and the air speed. It allows conclude that the use of cooler is necessary because it decrease significantly the thermal resistance when the speed air is thereabout 2 m/s. Fig.4 (d) exhibit the relation of thermal resistance as the length and the difference temperature ( T).

The datasheet of the heat-sink manufacturer show one curve of the thermal resistance in function of air speed, given (28). This curve consider one T=75oC and a length of 4’’, for other T and length the designer need use a

correction factor of temperature (F T) and a correction factor of length (FL), respectively (29) and (30).

( 0.9446 ) ( 0.04784 )21577 0.3661 0.1589Vel Vel

HSR e eθ− ⋅ − ⋅= ⋅ + ⋅ (28)

( 0.04873 ) ( 0.002477 )0.6859 1.183t ttF e e− ⋅Δ − ⋅Δ

Δ = ⋅ + ⋅ (29)

21577

HSswL

HS t

RF

R Fθ

θ Δ

=⋅

(30)

Finally, the length correction factor is substituted in (31) and then is possible find the length of heat-sink. The heat-sink volume is obtained made the product of the all dimension of heat-sink, (32).

3 2

8.239 1.7410

0.6121 0.2681 0.056L

L L L

FL

F F F⋅ −

= ⋅− ⋅ + ⋅ −

(31)

21.50 7.75HSswVol L= ⋅ ⋅ (32)

V. COMPARISON ANALYSIS

The comparison has the purpose of obtaining the carrier frequencies in which the three systems will present the same output filter, in other words, the output filter used in the three systems will present the same volume, weight and cost. These frequencies are obtained when the DF1 is equal for all systems.

The performance indexes: number of devices, number of levels of output phase voltage, carrier frequency, frequency of the first harmonic band, total harmonic distortion, first order distortion factor, semiconductor power losses, heat-sink volume and efficiency for each topology are shown in Table 2. These indexes were calculated using the amplitude modulation index equal 1.

Fig.5 (a), (b) and (c) presents respectively the semiconductors power losses distribution for the NPC, symmetrical and hybrid asymmetrical inverter. The total power losses for the NPC inverter are 6910W, for the symmetrical inverter are 1383W and for hybrid asymmetrical are 1027W. It is interesting that the NPC inverter has almost all its losses related with the switching. This occurs because the NPC inverter present less output voltage levels, and consequently it needs operate at frequency higher than other converters to obtain the same output filter.

Using the semiconductors power losses in each device, the thermal models of the semiconductors and the heat-sink profile provided in section IV is possible determine the length of the heat-sink for each device and module. In Fig.6 (a), (b) and (c) can be seen the total heat-sink volume for the NPC, symmetrical and hybrid asymmetrical inverter, respectively. The sum of all heat-sin length is equal to 133.74cm for the NPC inverter, equal to 129.12 cm for the symmetrical inverter and equal to 95.6 cm for the hybrid asymmetrical inverter. The sum of all heat-sink volume is equal to 22284 cm3 for the NPC inverter, equal to 21514 cm3 for the symmetrical inverter and equal to 15929 cm3 for the hybrid asymmetrical inverter.

Although the NPC inverter presented the power losses approximately five times highest that the symmetrical inverter the heat-sink volume is almost equal. This occurs because the thermal resistances of the

(a) (b)

(c) (d)

Figure 4. Heat-sink profile: (a) 3D view; (b) 1D view and measurements; (c) relation of thermal resistance with the length and

speed air; (d) relation of thermal resistance with the length and temperature variation

TABLE 1. THERMAL RESISTANCES OF DEVICES AND MODULES

BSM200 FZ200 DG408 DSF8045 R j-c_sw (K/W) 0.075 0.033 0.069 --- R j-c_d (K/W) 0.15 0.063 --- 0.09 R c-hs (K/W) 0.01 0.016 0.009 0.02

TABLE 2. COMPENDIUM OF THE COMPARISON

Topologies NPC 1-1-1-1 1-1-2 Total number of devices/phase 6 16 12 Number of phase-voltage levels 2 9 9

Carrier frequency [Hz] 5580 240 1860 Freq. of first harmonic band [Hz] 5580 1920 1860

THD [%] 56.47 13.57 13.90 DF1 [%] 0.4686 0.4697 0.4613

Total power losses/phase [W] 6910 1383 1027 Total heat-sink length/phase [cm] 133.74 129.12 95.6

Heat-sink volume/phase [cm3] 22284 21514 15929 Efficiency [%] 95.25 99.18 99.38

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FZ200R65KF1 module are very smallest than the thermal resistances of the BSM200GB170DLC module.

The association of the GTO for the highest power cell and IGBT for the smallest power cells in the hybrid asymmetrical inverter make that this converter presents the smallest power losses and the smallest heat-sink volume.

VI. EXPERIMENTAL RESULTS

This section presents the experimental results obtained with a low-power prototype of one phase of a hybrid asymmetric nine-level inverter. This multilevel inverter uses three H-bridge cells in series and its nominal output power is 1 kW. The isolated DC voltage sources are: VDC1=85V, VDC2=85V and VDC3=170V. These DC voltage sources are implemented using a multipulse transformer and 4 three-phase rectifiers, where the nominal load of each rectifier is: P1=133W, P2=230W, P3=318,5W and P4=318,5W. The voltage DC source of the cell 3 is obtained with two series-connected rectifiers (rectifiers 3 and 4). Details about the multipulse transformer design can be verified in [15].

All H-bridge cells are implemented using the IGBT module SK45GB063 (600V/30A). The mathematical models of the SK45GB063, vce(iload(θ)), vF(iload(θ)),Eon(iload(θ)), Eoff(iload(θ)) and Erec(iload(θ)) are given by:

45

(0.008045 ( )) ( 0.09678 ( ))1.598 1.573l l

SK

I Icev e eθ θ⋅ − ⋅= ⋅ − ⋅ (33)

45

(0.005818 ( )) ( 0.1285 ( ))1.016 1.012l l

SK

I IFv e eθ θ⋅ − ⋅= ⋅ − ⋅ (34)

( )45

(0.058 ( )) (0.059 ( )) 33.31 2.93 10l l

SK

I IonE e eθ θ⋅ ⋅ −= ⋅ − ⋅ ⋅ (35)

( )45

( 0.0038 ( )) ( 0.0077 ( )) 310.3 10.1 10l l

SK

I IoffE e eθ θ− ⋅ − ⋅ −= ⋅ − ⋅ ⋅ (36)

( )45

( 0.006 ( )) ( 0.012 ( )) 32.69 2.63 10l l

SK

I IrecE e eθ θ− ⋅ − ⋅ −= ⋅ − ⋅ ⋅ (37)

The power losses of each cell are computed from the mathematical model of each semiconductor. The efficiencies found for cells 3, 2 and 1 are 98.83%, 96.73% and 92.97%, respectively. The total efficiency is 97.59%.

Fig. 8, Fig. 9 and Fig. 10 present the experimental results obtained with the prototype. The measures were made with the Digital Power Meter WT1600 (Yokogawa).

Fig. 8 presents the measurements of input and output of each cell of the 1-1-2 inverter, where: UrmsX, IrmsX and PX represent, respectively, the voltage, current and active power of each channel X. The channels 1, 2 and 3 represent the input measurements of the cells 1, 2 and 3, while the channels 4, 5 and 6 represent the output measurements of these cells. The parameters F1, F2 and F3 are the efficiency of the cells 1, 2 and 3. P A is the total input active power, P B is the total output active power and is the total efficiency of the converter.

The efficiency of the each H-bridge cell obtained in the prototype can see in the Fig. 8, where de efficiency of the cells 3, 2 and 1 are, respectively, 96.853%, 94.150% and 93.817%. The total efficiency is 95.57%. There is a difference between the theoretical and experimental results obtained from the prototype. However, this difference can be caused by the gate resistance. The theoretical efficiencies are similar to the experimental efficiencies. The difference between the theoretical and experimental results not affects the conclusion of this paper because the errors that occur for one topology also happen in the other.

0

750

1500

2250

3000

3750Po

wer

Los

ses [

W]

Switch1

Switch2

Switch3

Switch4

Diode 5

Diode 6

PrecPoffPonPcondDPcondSW

(a)

0

1250

2500

3750

5000

6250

Vol

ume

[cm3 ]

Switch1

Switch2

Switch3

Switch4

Diode5

Diode6

(a)

0

75

150

225

300

375

Pow

er L

osse

s [W

]

Cell 4 Cell 3 Cell 2 Cell 1

PrecPoffPonPcondDPcondSW

(b)

0

1250

2500

3750

5000

6250

Vol

ume

[cm3 ]

Cell 4 Cell 3 Cell 2 Cell 1

Module 2Module 1

(b)

0

100

200

300

400

500

Pow

er L

osse

s [W

]

Cell 3 Cell 2 Cell 1

PrecPoffPonPcondDPcondSW

(c)Figure 5. Power losses distribution: (a) NPC; (b) 1-1-1-1; (c) 1-1-2

0

2500

5000

7500

10000

12500V

olum

e [c

m3 ]

Cell 3 Cell 2 Cell 1

Module 2Module 1

(c)Figure 6. Heat-sink volume: (a) NPC; (b) 1-1-1-1; (c) 1-1-2

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Fig. 9 presents the output voltage waveforms of the cells 1, 2 and 3, likewise that the output phase-voltage of the 1-1-2 inverter.

Fig. 10 shows the trends of the efficiency of each cell and of the total efficiency. The trend efficiency of the cell 1, 2, 3 and total are given respectively by T1, T2, T3 and T6. These measurements were made to amplitude modulation indexes equal to 0.065, 0.09, 0.11, 0.17, 0.22,

0.31, 0.47, 0.63, 0.79 and 1. Fig. 10 proves that the cell 1 presents the worst efficiency because it operates in high frequency and the cell 3 presents the best efficiency because it operates in low frequency.

VII. CONCLUSION

This paper presents the comparison among three topologies of multilevel inverters. Among two nine levels inverters with H-bridge cells connected in series, one configuration is hybrid and asymmetrical (1-1-2) and the other is symmetrical (1-1-1-1) and the NPC inverter. The comparison is developed with the purpose of finding the efficiency and the heat-sink volume where the three systems present the same output filter. In the comparison, the topology hybrid and asymmetrical (1-1-2) presents lowest power losses and smallest heat-sink volume. Although the neutral point clamped inverter (NPC) presents higher power losses the heat-sink volume is similar to the symmetric topology (1-1-1-1).

REFERENCES

[1] Kim,T. J., Kang, D. W., Lee, Y. H., Hyun, D. S., “The Analysis of Conduction and Switching Losses in Multi-Level Inverter System”, in Proc. of the 32th Power Electronics Specialists Conference and Applications, pp. 1363-1368, 2001.

[2] Massoud, A. M., Finney, S. J., Williams, B. W., “Multilevel Converters and Series Connection of IGBT Evaluation for High-Power, High-Voltage Applications”, in Proc. of the 2nd Power Electronics, Machines and Drives Conference, pp. 1-5, 2004.

[3] Bernet, S., Krug, D., Fazel, S. S., Jalili, K., “Design and Comparison of 4.16kV Neutral Point Clamped, Flying Capacitor and Series Connected H-Bridge Multi-Level Converters”, in Proc. of the 40th Industry Applications Conference, pp. 121-128, 2005.

[4] Zambra, D. A. B., Rech, C., Pinheiro, J. R., “Selection of DC Sources for Three Cells Cascaded H-Bridge Hybrid Multilevel Inverter Applied to Medium Voltage Induction Motors”, inProc.of the 8th Brazilian Power Electronics Conference, 2005.

[5] Zambra, D.A.B, Rech, C., Pinheiro, J.R., “A comparative analysis between the symmetric and the hybrid asymmetric nine-level series connected H-bridge cells inverter”, Proc. of the 12th European Conference on Power Electronics and Applications, pp. 1−10, 2007.

[6] Zambra, D.A.B, Rech, C., Pinheiro, J.R., “Comparison Among Three Topologies of Multilevel Inverters”, Proc. of the 9th Brazilian Power Electronics Conference, Blumenau, pp. 528−533, 2007.

[7] Eupec, Technical Informations: IGBT - Module FZ200R65KF1, p.10, 2002.

[8] Eupec, Technical Informations: IGBT – Module BSM200GB170DLC, p.9, 2002.

[9] Dynex Semiconductors, Data Sheet: Gate Turn-off Thyristor – DG408BP45, p.19, 2000.

[10] Dynex Semiconductors, Data Sheet: Fast Recovery Diode – DSF8045SK, p.7, 2004

[11] Agelidis, V. G., Calais, M., “Application specific harmonic performance evaluation of multicarrier PWM techniques”. Proc. of the 29th Power Electronics Specialists Conference and Applications, pp. 172–178, 1998.

[12] Calais, M., Borle, L. J., Agelidis, V. G., “Analysis of multicarrier PWM methods for a single-phase five level inverter”. Proc. of the 32th Power Electronics Specialists Conference and Applications,pp. 1351–1356, 2001.

[13] Williams, B.W. Power Electronics - Devices, Drives, Applications and Passive Components, ed. Palgrave Macmillan. pp. 715p, 2006.

[14] HS Dissipadores. Catalogo HS Disspadores. p. 118, 2007. [15] Rech, C., Pinheiro, J.R., “Line current harmonics reduction in

multipulse connection of asymmetrically loaded rectifiers”. IEEE Transactions on Industrial Electronics, Vol. 22, no 3, 2005 pp. 967-977

Figure 8. Measurements of the converter

Figure 9. Output voltage waveform of cells 1, 2, 3 and of the phase-voltage

Figure 10. Efficiency trend of the cells 1, 2,3 and total.