Microeletrônica - PUCRS

Microeletrônica

q Professor: Fernando Gehm Moraesq Livro texto:

Digital Integrated Circuits a Design Perspective - RabaeyC MOS VLSI Design - Weste

Revisão das lâminas: 15/março/2022

Aula #2 à Inversor - comportamento estático e dinâmico

Portas Lógicas Digitais: Parâmetros Fundamentais

Inversor

• Funcionalidade• Robusteza, Confiabilidade• Área• Desempenho

Velocidade (atraso)Dissipação de PotênciaConsumo de Energia

2

Ruído em Circuitos Integrados DigitaisInversor

Acoplamento Indutivo Acoplamento Capacitivo Ruído de Alimentação

Fontes de ruído (figura 1.10):

Ruído significa variação indesejada de tensão ou de corrente nos nós lógicos

3

Section 4.4 Electrical Wire Models 159

cuitry. Typical values of the characteristic impedance of wires in semiconductor circuitsrange from 10 to 200 Ω.

Example 4.10 Propagation Speeds of Signal WaveformsThe information of Table 4.6 shows that it takes 1.5 nsec for a signal wave to propagate fromsource-to-destination on a 20 cm wire deposited on an epoxy printed-circuit board. If trans-mission line effects were an issue on silicon integrated circuits, it would take 0.67 nsec for thesignal to reach the end of a 10 cm wire.

WARNING: The characteristic impedance of a wire is a function of the overall intercon-nect topology. The electro-magnetic fields in complex interconnect structures tend to beirregular, and are strongly influenced by issues such as the current return path. Providing ageneral answer to the latter problem has so far proven to be illusive, and no closed-formedanalytical solutions are typically available. Hence, accurate inductance and characteristicimpedance extraction is still an active research topic. For some simplified structures,approximative expressions have been derived. For instance, the characteristic impedancesof a triplate strip-line (a wire embedded in between two ground planes) and a semiconduc-tor micro strip-line (wire above a semiconductor substrate) are approximated by Eq. (4.29)and Eq. (4.30), respectively.

(4.29)

and

(4.30)

Termination

The behavior of the transmission line is strongly influenced by the termination of the line.The termination determines how much of the wave is reflected upon arrival at the wire

Figure 4.18 Propagation of voltage step along a lossless transmission line.Direction of propagation

Wire

Substrate

x

dx

I

V

Z0 triplate( ) 94Ωµrεr----- 2t W+

H W+---------------- ln≈

Z0 microstrip( ) 60Ωµr

0.475εr 0.67+----------------------------------- 4t

0.536W 0.67H+---------------------------------------- ln≈

chapter4.fm Page 159 Friday, January 18, 2002 9:00 AM

24 INTRODUCTION Chapter 1

expected response. One reason for this aberration are the variations in the manufacturingprocess. The dimensions, threshold voltages, and currents of an MOS transistor varybetween runs or even on a single wafer or die. The electrical behavior of a circuit can beprofoundly affected by those variations. The presence of disturbing noise sources on or offthe chip is another source of deviations in circuit response. The word noise in the contextof digital circuits means “unwanted variations of voltages and currents at the logicnodes.” Noise signals can enter a circuit in many ways. Some examples of digital noisesources are depicted in Figure 1.10. For instance, two wires placed side by side in an inte-grated circuit form a coupling capacitor and a mutual inductance. Hence, a voltage or cur-rent change on one of the wires can influence the signals on the neighboring wire. Noiseon the power and ground rails of a gate also influences the signal levels in the gate.

Most noise in a digital system is internally generated, and the noise value is propor-tional to the signal swing. Capacitive and inductive cross talk, and the internally-generatedpower supply noise are examples of such. Other noise sources such as input power supplynoise are external to the system, and their value is not related to the signal levels. For thesesources, the noise level is directly expressed in Volt or Ampere. Noise sources that are afunction of the signal level are better expressed as a fraction or percentage of the signallevel. Noise is a major concern in the engineering of digital circuits. How to cope with allthese disturbances is one of the main challenges in the design of high-performance digitalcircuits and is a recurring topic in this book.

The steady-state parameters (also called the static behavior) of a gate measure howrobust the circuit is with respect to both variations in the manufacturing process and noisedisturbances. The definition and derivation of these parameters requires a prior under-standing of how digital signals are represented in the world of electronic circuits.

Digital circuits (DC) perform operations on logical (or Boolean) variables. A logicalvariable x can only assume two discrete values:

x ∈ 0,1

As an example, the inversion (i.e., the function that an inverter performs) implements thefollowing compositional relationship between two Boolean variables x and y:

y = x: x = 0 ⇒ y = 1; x = 1 ⇒ y = 0 (1.6)

VDDv(t)

i(t)

(a) Inductive coupling (b) Capacitive coupling

Figure 1.10 Noise sources in digital circuits.

(c) Power and ground noise



expected response. One reason for this aberration are the variations in the manufacturingprocess. The dimensions, threshold voltages, and currents of an MOS transistor varybetween runs or even on a single wafer or die. The electrical behavior of a circuit can beprofoundly affected by those variations. The presence of disturbing noise sources on or offthe chip is another source of deviations in circuit response. The word noise in the contextof digital circuits means “unwanted variations of voltages and currents at the logicnodes.” Noise signals can enter a circuit in many ways. Some examples of digital noisesources are depicted in Figure 1.10. For instance, two wires placed side by side in an inte-grated circuit form a coupling capacitor and a mutual inductance. Hence, a voltage or cur-rent change on one of the wires can influence the signals on the neighboring wire. Noiseon the power and ground rails of a gate also influences the signal levels in the gate.

Most noise in a digital system is internally generated, and the noise value is propor-tional to the signal swing. Capacitive and inductive cross talk, and the internally-generatedpower supply noise are examples of such. Other noise sources such as input power supplynoise are external to the system, and their value is not related to the signal levels. For thesesources, the noise level is directly expressed in Volt or Ampere. Noise sources that are afunction of the signal level are better expressed as a fraction or percentage of the signallevel. Noise is a major concern in the engineering of digital circuits. How to cope with allthese disturbances is one of the main challenges in the design of high-performance digitalcircuits and is a recurring topic in this book.

The steady-state parameters (also called the static behavior) of a gate measure howrobust the circuit is with respect to both variations in the manufacturing process and noisedisturbances. The definition and derivation of these parameters requires a prior under-standing of how digital signals are represented in the world of electronic circuits.

Digital circuits (DC) perform operations on logical (or Boolean) variables. A logicalvariable x can only assume two discrete values:

x ∈ 0,1

As an example, the inversion (i.e., the function that an inverter performs) implements thefollowing compositional relationship between two Boolean variables x and y:

y = x: x = 0 ⇒ y = 1; x = 1 ⇒ y = 0 (1.6)

VDDv(t)

i(t)

(a) Inductive coupling (b) Capacitive coupling

Figure 1.10 Noise sources in digital circuits.

(c) Power and ground noise


Porta IdealInversor

Ventrada

Vsaída

g = ∞

RI = ∞RO = 0

4

OutIn

VDD

PMOS

NMOS


Fan-In and Fan-Out

The fan-out denotes the number of load gates N that are connected to the output of thedriving gate (Figure 1.16). Increasing the fan-out of a gate can affect its logic output lev-els. From the world of analog amplifiers, we know that this effect is minimized by makingthe input resistance of the load gates as large as possible (minimizing the input currents)and by keeping the output resistance of the driving gate small (reducing the effects of loadcurrents on the output voltage). When the fan-out is large, the added load can deterioratethe dynamic performance of the driving gate. For these reasons, many generic and librarycomponents define a maximum fan-out to guarantee that the static and dynamic perfor-mance of the element meet specification.

The fan-in of a gate is defined as the number of inputs to the gate (Figure 1.16b).Gates with large fan-in tend to be more complex, which often results in inferior static anddynamic properties.

The Ideal Digital Gate

Based on the above observations, we can define the ideal digital gate from a static per-spective. The ideal inverter model is important because it gives us a metric by which wecan judge the quality of actual implementations.

Its VTC is shown in Figure 1.17 and has the following properties: infinite gain in thetransition region, and gate threshold located in the middle of the logic swing, with highand low noise margins equal to half the swing. The input and output impedances of theideal gate are infinity and zero, respectively (i.e., the gate has unlimited fan-out). Whilethis ideal VTC is unfortunately impossible in real designs, some implementations, such asthe static CMOS inverter, come close.

Example 1.5 Voltage-Transfer CharacteristicFigure 1.18 shows an example of a voltage-transfer characteristic of an actual, but outdatedgate structure (as produced by SPICE in the DC analysis mode). The values of the dc-param-eters are derived from inspection of the graph.

N

M

Figure 1.16 Definition of fan-out and fan-in of a digital gate.(a) Fan-out N

(b) Fan-in M


Section 1.3 Quality Metrics of a Digital Design 31

VOH = 3.5 V; VOL = 0.45 V

VIH = 2.35 V; VIL = 0.66 V

VM = 1.64 V

NMH = 1.15 V; NML = 0.21 V

The observed transfer characteristic, obviously, is far from ideal: it is asymmetrical,has a very low value for NML, and the voltage swing of 3.05 V is substantially below the max-imum obtainable value of 5 V (which is the value of the supply voltage for this design).

1.3.3 Performance

From a system designers perspective, the performance of a digital circuit expresses thecomputational load that the circuit can manage. For instance, a microprocessor is oftencharacterized by the number of instructions it can execute per second. This performance

Vin

Vout

Figure 1.17 Ideal voltage-transfer characteristic.

g = -∞

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

1.0

2.0

3.0

4.0

5.0

Vou

t (V

)

Figure 1.18 Voltage-transfer characteristic of an NMOS inverter of the 1970s.

VM

NMH

NML


InversorOperação DC: Característica de Transferência de Tensão

V(y)

V(x) = V(y)

V(x)

V(x)

V(y)

VOH

VOL

VMthreshold de chaveamento

VIL VIH

níveis nominais de tensão

f

VM = tensão de thresholdde chaveamento

OBS: Não confundir com VT queé a tensão de threshold do transistor

è Qual o valor “ideal” para VM ?5

OutIn

VDD

PMOS

NMOS

InversorMapeamento entre sinais analógicos e digitais

V(x)

V(y)

VOH

VOL

VIL VIH

f

inclinação = - 1

inclinação = - 1

VOH

VOL

VIL

VIH

regiãoindefinida

1

0Quanto maiores as regiões “0” e “1’ maior imunidade ao ruído

6

OutIn

VDD

PMOS

NMOS

Resposta EstáticaInversor CMOS

• Excursão da saída igual aos valores da alimentação

• Os níveis lógicos não dependem do dimensionamento dos transistores

• Baixa impedância de saída (< 10 kW) – ideal: zero

• Altíssima resistência de entrada – ideal: infinita• Curva de transferência de tensão (VTC) simétrica• Tempo de propagação do sinal é função:

• capacitância de carga• resistência dos transistores

• Não há dissipação de potência estática• Caminho de corrente direto durante o chaveamento

7

8

2.5 DC Transfer Characteristics 89

OFF, leaving the nMOS transistor to pull the output down to GND. Also notice that theinverter’s current consumption is ideally zero, neglecting leakage, when the input is withina threshold voltage of the VDD or GND rails. This feature is important for low-poweroperation.

Figure 2.27 shows simulation results of an inverter from a 65 nm process. ThepMOS transistor is twice as wide as the nMOS transistor to achieve approximatelyequal betas. Simulation matches the simple models reasonably well, although the tran-sition is not quite as steep because transistors are not ideal current sources in saturation.

The crossover point where Vinv = Vin = Vout is called the input threshold. Becauseboth mobility and the magnitude of the threshold voltage decrease with temperaturefor nMOS and pMOS transistors, the input threshold of the gate is only weaklysensitive to temperature.

TABLE 2.3 Summary of CMOS inverter operation

Region Condition p-device n-device OutputA 0 f Vin < Vtn linear cutoff Vout = VDD

B Vtn f Vin < VDD/2 linear saturated Vout > VDD /2

C Vin = VDD/2 saturated saturated Vout drops sharply

D VDD /2 < Vin f VDD – |Vtp| saturated linear Vout < VDD/2

E Vin > VDD – |Vtp| cutoff linear Vout = 0

C

Vgsn5

Vgsn4

Vgsn3

Vgsn2Vgsn1

Vgsp5

Vgsp4

Vgsp3

Vgsp2

Vgsp1

VDD

–VDD

Vdsn

–Vdsp

–Idsp

Idsn

0

Vin5

Vin4

Vin3

Vin2Vin1

Vin0

Vin1

Vin2

Vin3Vin4

Idsn, |I |dsp

Vout

VDD

Vout

0 Vin

VDD

(a)

(b)

(c)

(d)

IDD

0

Vin

VDD

A B

DE

0

VDDVtn

VDD–|Vtp|

VDD/2

FIGURE 2.26 Graphical derivation of CMOS inverter DC characteristic

0.2

0.4

0.6

1.0

0.0

0.8

0.0 0.2 0.4 0.6 0.8 1.0Vin

Vout

FIGURE 2.27 Simulated CMOS inverter DC characteristic

Fonte: weste

Static CMOS Inverter DC Characteristics

Chapter 2 MOS Transistor Theory88

2.5.1 Static CMOS Inverter DC CharacteristicsLet us derive the DC transfer function (Vout vs. Vin) for the static CMOS inverter shownin Figure 2.25. We begin with Table 2.2, which outlines various regions of operation forthe n- and p-transistors. In this table, Vtn is the threshold voltage of the n-channel device,and Vtp is the threshold voltage of the p-channel device. Note that Vtp is negative. Theequations are given both in terms of Vgs /Vds and Vin /Vout. As the source of the nMOStransistor is grounded, Vgsn = Vin and Vdsn = Vout. As the source of the pMOS transistor istied to VDD, Vgsp = Vin – VDD and Vdsp = Vout – VDD.

The objective is to find the variation in output voltage (Vout) as a function of the inputvoltage (Vin). This may be done graphically, analytically (see Exercise 2.16), or throughsimulation [Carr72]. Given Vin, we must find Vout subject to the constraint that Idsn =|Idsp|. For simplicity, we assume Vtp = –Vtn and that the pMOS transistor is 2–3 timesas wide as the nMOS transistor so Gn = Gp. We relax this assumption in Section 2.5.2.

We commence with the graphical representation of the simple algebraic equationsdescribed by EQ (2.10) for the two transistors shown in Figure 2.26(a). The plot showsIdsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and Vgsp. Figure 2.26(b)shows the same plot of Idsn and |Idsp| now in terms of Vout for various values of Vin. Thepossible operating points of the inverter, marked with dots, are the values of Vout whereIdsn = |Idsp| for a given value of Vin. These operating points are plotted on Vout vs. Vin axesin Figure 2.26(c) to show the inverter DC transfer characteristics. The supply current IDD= Idsn = |Idsp| is also plotted against Vin in Figure 2.26(d) showing that both transistorsare momentarily ON as Vin passes through voltages between GND and VDD, resulting ina pulse of current drawn from the power supply.

The operation of the CMOS inverter can be divided into five regions indicated on Fig-ure 2.26(c). The state of each transistor in each region is shown in Table 2.3. In region A, thenMOS transistor is OFF so the pMOS transistor pulls the output to VDD. In region B, thenMOS transistor starts to turn ON, pulling the output down. In region C, both transistorsare in saturation. Notice that ideal transistors are only in region C for Vin = VDD/2 and thatthe slope of the transfer curve in this example is – in this region, corresponding to infi-nite gain. Real transistors have finite output resistances on account of channel lengthmodulation, described in Section 2.4.2, and thus have finite slopes over a broader regionC. In region D, the pMOS transistor is partially ON and in region E, it is completely

TABLE 2.2 Relationships between voltages for the three regions of operation of a CMOS inverter

Cutoff Linear Saturated

nMOS Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vin < Vtn Vin > Vtn Vin > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

Vout < Vin – Vtn Vout > Vin – Vtn

pMOS Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vin > Vtp + VDD Vin < Vtp + VDD Vin < Vtp + VDD

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

Vout > Vin – Vtp Vout < Vin – Vtp

h

Idsn

IdspVout

VDD

Vin

FIGURE 2.25A CMOS inverter

Características de CargaInversor CMOS

PMOS NMOS

In,pVin = 5

Vin = 5

Vin = 4

Vin = 4

Vin = 3Vin = 3

Vin = 3

Vin = 2 Vin = 2

Vin = 2

Vin =1

Vin = 1

Vin = 0

Vin = 0

Vout

Curva de cargas dos transistores N e P

Pontos válidos In = Ip (dado que eles estão em série ente Vcc e Gnd)

9

OutIn

VDD

PMOS

NMOS


PMOS NMOS

In,p Vin = 5

Vin = 5

Vin = 4

Vin = 4

Vin = 3Vin = 3

Vin = 3

Vin = 2 Vin = 2

Vin = 2

Vin =1

Vin = 1

Vin = 0

Vin = 0

Vout

Vin=0:

Saída = Vdd

TransistorN e TransisorP com corrente = 0

10

OutIn

VDD

PMOS

NMOS


PMOS NMOS

In,p Vin = 5

Vin = 5

Vin = 4

Vin = 4

Vin = 3Vin = 3

Vin = 3

Vin = 2 Vin = 2

Vin = 2

Vin =1

Vin = 1

Vin = 0

Vin = 0

Vout

Vin=1:

Saída ainda próxima de vdd

Início de condução do transistor N

11

OutIn

VDD

PMOS

NMOS


PMOS NMOS

In,p Vin = 5

Vin = 5

Vin = 4

Vin = 4

Vin = 3Vin = 3

Vin = 3

Vin = 2 Vin = 2

Vin = 2

Vin =1

Vin = 1

Vin = 0

Vin = 0

Vout

Vin=3:

Passagem abrupta para saída próxima de zero

12

OutIn

VDD

PMOS

NMOS

Inversor CMOS Curvas de Transferência de Tensão (VTC)

13

OutIn

VDD

PMOS

NMOS

Inversor CMOS Corrente com carga de saída

I(p)

I(n)

I(out) Corrente na saída

V(in)

Descarga(corrente pelo N)

Carga(corrente pelo P)

Diferentes rampas de entrada

Entrada 0 satura o TP

Entrada 1 satura o TnV(out)

OutIn

VDD

PMOS

NMOS

Inversor CMOS Efeito da rampa

V(in) Diferentes rampas de entrada

Entrada 0 satura o TP

Entrada 1 satura o TnV(out)

td = 19.689 psts = 18.981 pstot_power = 2.82e-06

Rampa “rápida” (baixo slew)

td = 49.1946 psts = 52.0563 pstot_power = 3.87e-06 (+37%)

Rampa “lenta” (alto slew)

Variação do Tamanho do Transistor - W

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

V out(V)

Nominal

Valor de entradaabaixo de vcc/2 passade ‘1’ para ‘0’. Logo, éo transistor N que estácom maior ganho:

Wp/Wn < µn/µp

Exemplo: Wp=4 e Wn=2

Nominal: relação entre Wp/Wn igual a relação da mobilidade µn/µp. Exemplo:- Wp= 6, Wn=2 e µn/µp=3

Valor de entradaacima de vcc/2 passade ‘0’ para ‘1’. Logo, éo transistor P que estácom maior ganho:

Wp/Wn > µn/µp

Exemplo: Wp=8 e Wn=2

16

OutIn

VDD

PMOS

NMOS

Saíd

a -V

out

Entrada - Vin

Aumento de Wp

VTp = -1.4

17

0,6/0,58

Zoom mostrando ochaveamento na meia

excursão do sinal de entrada

InversorPropriedade de Regeneração

cadeia de inversores

Inversor pode ser visto como um amplificador

18


turbed signal gradually converges back to one of the nominal voltage levels after passingthrough a number of logical stages. This property can be understood as follows:

An input voltage vin (vin ∈ “0”) is applied to a chain of N inverters (Figure 1.14a).Assuming that the number of inverters in the chain is even, the output voltage vout (N →∞) will equal VOL if and only if the inverter possesses the regenerative property. Similarly,when an input voltage vin (vin ∈ “1”) is applied to the inverter chain, the output voltagewill approach the nominal value VOH.

Example 1.4 Regenerative property

The concept of regeneration is illustrated in Figure 1.14b, which plots the simulated transientresponse of a chain of CMOS inverters. The input signal to the chain is a step-waveform with

Figure 1.13 Cascaded inverter gates: definition of noise margins.

VIH

VIL

Undefinedregion

“1”

“0”

VOH

VOL

NMH

NML

Gate output Gate input

Stage M Stage M + 1

(a) A chain of inverters

Figure 1.14 The regenerative property.

v0 v1 v2 v3 v4 v5 v6

…

0 2 4 6 8 10t (nsec)

–1

1

3

5

V (V

olt) v0

v1 v2

(b) Simulated response of chain of MOS inverters

chapter1.fm Page 27 Friday, January 18, 2002 8:58 AMSection 1.3 Quality Metrics of a Digital Design 27






VIH

VIL

Undefinedregion

“1”

“0”

VOH

VOL

NMH

NML


Stage M Stage M + 1



v0 v1 v2 v3 v4 v5 v6

…

0 2 4 6 8 10t (nsec)

–1

1

3

5

V (V

olt) v0

v1 v2




cadeia de inversores

Vout

Vin

Vout

Vin

Inversor pode ser visto como um amplificador

porta com regeneração(alta margem de ruído)

porta sem regeneração(baixa margem de ruído) 19







VIH

VIL

Undefinedregion

“1”

“0”

VOH

VOL

NMH

NML


Stage M Stage M + 1



v0 v1 v2 v3 v4 v5 v6

…

0 2 4 6 8 10t (nsec)

–1

1

3

5

V (V

olt) v0

v1 v2



V1

V00 ruim

V0V1 V2 V3 V4

V2

V1

V3

V2

V4

V30 bo

m

porta com regeneração- recuperação do nível alto- Propriedade de amplificação

20

V0 V1 V2 V3

V0 (0.59 – 0.61 V)

V1 (0.50 – 0.67 V)

V2 (0.10 – 1.1 V)


21

V3 (0 – 1.2 V)

Excursão do sinal de entrada: 0 e 1.2 V

Entrada muito “ruim”, próxima à meia excursão do sinal de entrada

V1

V00 ruim

V0V1 V2 V3 V4

V2

V1

V3

V2

V4

V3

porta sem regeneração- não recupera o nível alto

22


porta com regeneração(alta margem de ruído)

porta sem regeneração(baixa margem de ruído) 23







VIH

VIL

Undefinedregion

“1”

“0”

VOH

VOL

NMH

NML


Stage M Stage M + 1



v0 v1 v2 v3 v4 v5 v6

…

0 2 4 6 8 10t (nsec)

–1

1

3

5

V (V

olt) v0

v1 v2




a degraded amplitude, which could be caused by noise. Instead of swinging from rail to rail,v0 only extends between 2.1 and 2.9 V. From the simulation, it can be observed that this devi-ation rapidly disappears, while progressing through the chain; v1, for instance, extends from0.6 V to 4.45 V. Even further, v2 already swings between the nominal VOL and VOH. Theinverter used in this example clearly possesses the regenerative property.

The conditions under which a gate is regenerative can be intuitively derived by ana-lyzing a simple case study. Figure 1.15(a) plots the VTC of an inverter Vout = f(Vin) as wellas its inverse function finv(), which reverts the function of the x- and y-axis and is definedas follows:

(1.9)

Assume that a voltage v0, deviating from the nominal voltages, is applied to the firstinverter in the chain. The output voltage of this inverter equals v1 = f(v0) and is applied tothe next inverter. Graphically this corresponds to v1 = finv(v2). The signal voltage gradu-ally converges to the nominal signal after a number of inverter stages, as indicated by thearrows. In Figure 1.15(b) the signal does not converge to any of the nominal voltage levelsbut to an intermediate voltage level. Hence, the characteristic is nonregenerative. The dif-ference between the two cases is due to the gain characteristics of the gates. To be regener-ative, the VTC should have a transient region (or undefined region) with a gain greaterthan 1 in absolute value, bordered by the two legal zones, where the gain should besmaller than 1. Such a gate has two stable operating points. This clarifies the definition ofthe VIH and the VIL levels that form the boundaries between the legal and the transientzones.

Noise Immunity

While the noise margin is a meaningful means for measuring the robustness of a circuitagainst noise, it is not sufficient. It expresses the capability of a circuit to “overpower” a

in f out( ) in⇒ finv out( )= =

Figure 1.15 Conditions for regeneration.

in

out out

in

(a) Regenerative gate

f(v)

finv(v)

finv(v)

f(v)

(b) Nonregenerative gate

v3

v1

v2 v0 v0 v2

v3

v1


Definição de AtrasosInversor

t

ttpHL tpLH

tf tr

50%

10%

50%

90%

Vin

Vout

tpHL = tempo de propagação 1 0

tpLH = tempo de propagação 0 1

tf = tempo de descida

tr = tempo de subida

tp = tpLH + tpHL

2

24

Oscilador em AnelInversor

V0 V1 V2 V3 V4 V5

V0 V1 V5

tT = 2 x tp x N T = período do oscilador

25

Considere um oscilador em anel de 5 estágios, tendo o inversor tr=2,6 ns (tempo de propagação de subida de um inversor) e tf=1,4 ns (tempo de propagação de descida de um inversor).

T (período)

t1 t2

tempo

V(S)

’0’

1,4 ’0’ 2,6 ’1’ 1,4 ’0’ 2,6 ’1’ 1,4 0’ 2,6 ’1’ 1,4 ’0’ 2,6 ’1’ 1,4 ’0’ 2,6 ’1’

Fica em ’1’ por 9,4 nsFica em ’0’ por 10,6 ns

10,6 9,4

T = 20 ns

f = 50 MHz

Oscilador com 15 estágios

.measure tran tf trig v(n) val=0.6 td=1n rise = 10+ targ v(o) val=0.6 fall = 10.measure tran tr trig v(n) val=0.6 td=1n fall = 10+ targ v(o) val=0.6 rise = 10

RESULTADO:tf = 1.31323e-11tr = 1.29394e-11

Dica:

.ic v(a)=1.2

Tp = 12,986 ps

T = 2 * Tp * 15 = 389,576 ps

27

a b c d e f g h i j k l m n o

Tempo de propagação de um inversor

389.576 ps

2.57 GHz

Oscilador com 15 estágios

.measure tran tf trig v(n) val=0.6 td=1n rise = 10+ targ v(o) val=0.6 fall = 10.measure tran tr trig v(n) val=0.6 td=1n fall = 10+ targ v(o) val=0.6 rise = 10

.measure tran periodo param = '(tf+tr) * 1e9 * 15'

.measure tran freq param = '1/periodo’

Medindo diretamente o período:.measure tran periodo_o trig v(o) val=0.6 td=1n rise = 2+ targ v(o) val=0.6 rise = 3

28

a b c d e f g h i j k l m n o

Tempo de propagação de um inversor

freq = 2.56689 è frequência de oscilação igual a 2,57 GHzperiodo = 0.389576periodo_o = 3.89551 e-10

Resultado do measure

Sub-threshold

29

Vcc=1.0 à tp ≈12 ps

Vcc=0.2 à tp ≈1.8 ns = 1800 ps

Funciona corretamente, mas• 150x mais lento• baixíssima margem de ruído

M1 vcc iv out vcc psvtgp w=wp l=0.06M2 0 iv out 0 nsvtgp w=wn l=0.06

vcc vcc 0 dc 0.2vin1 iv 0 pulse (0.2 0 0 0.05N 0.05N 100n 200n)

C1 out 0 4fF

Measurement Name : transient1Analysis Type : trandiff = -154.777phl = 1.71937e-09plh = 1.87415e-09

CMOS Inverter

OutIn

VDD

PMOS

NMOS

A parte de imagem com identificação de relação rId4 não foi encontrada no arquivo.

Polysilicon

In Out

VDD

GND

PMOS

Metal 1

NMOS

Contacts

N Well

30

CMOS Inverter OutIn

VDD

PMOS

NMOS

31http://cmosedu.com/jbaker/courses/ee421L/f13/students/lamorea3/Lab5/lab5.html

CMOS Inverter

32

194 THE CMOS INVERTER Chapter 5

This physical information can be combined with the approximations derived above tocome up with an estimation of CL. The capacitor parameters for our generic process weresummarized in Table 3.5, and repeated here for convenience:

Overlap capacitance: CGD0(NMOS) = 0.31 fF/µm; CGDO(PMOS) = 0.27 fF/µmBottom junction capacitance: CJ(NMOS) = 2 fF/µm2; CJ(PMOS) = 1.9 fF/µm2

Side-wall junction capacitance: CJSW(NMOS) = 0.28 fF/µm; CJSW(PMOS) = 0.22 fF/µmGate capacitance: Cox(NMOS) = Cox(PMOS) = 6 fF/µm2

Finally, we should also consider the capacitance contributed by the wire, connectingthe gates and implemented in metal 1 and polysilicon. A layout extraction program typically

Table 5.1 Inverter transistor data.

W/L AD (µm2) PD (µm) AS (µm2) PS (µm)

NMOS 0.375/0.25 0.3 (19 λ2) 1.875 (15λ) 0.3 (19 λ2) 1.875 (15λ)

PMOS 1.125/0.25 0.7 (45 λ2) 2.375 (19λ) 0.7 (45 λ2) 2.375 (19λ)

Figure 5.15 Layout of two chained, minimum-size inverters using SCMOS Design Rules (see alsoColor-plate 6).

Polysilicon

InOut

Metal 1

VDD

GND

0.25 µm = 2λ

PMOS

NMOS

(9λ/2λ)

(3λ/2λ)


Two Inverters

Connect in Metal

• Share power and ground

• Abut cells

VDD

33

Fan-in e Fan-outInversor

…

N

Fan-out

…M

Fan-in

34

CMOS Inverter Propagation Delay

tpHL = f(Ron.CL)= 0.69 RonCL

35

0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vou

t(V)

Transient Response

tp = 0.69 CL (Reqn+Reqp)/2

?

tpLH tpHL

36

InversorDissipação de Potência

• Potência de pico: importante para dimensionar as linhas de alimentação

• Potência média: importante para cálculo de dissipação de calor e de dimensionamento das baterias

• Componentes da correnete:– Estático: devido às correntes de fuga– Dinâmico: proporcional ao chaveamento do inversor

37


Depending upon the design problem at hand, different dissipation measures have tobe considered. For instance, the peak power Ppeak is important when studying supply-linesizing. When addressing cooling or battery requirements, one is predominantly interestedin the average power dissipation Pav. Both measures are defined in equation Eq. (1.14):

(1.14)

where p(t) is the instantaneous power, isupply is the current being drawn from the supplyvoltage Vsupply over the interval t ∈ [0,T], and ipeak is the maximum value of isupply over thatinterval.

The dissipation can further be decomposed into static and dynamic components. Thelatter occurs only during transients, when the gate is switching. It is attributed to thecharging of capacitors and temporary current paths between the supply rails, and is, there-fore, proportional to the switching frequency: the higher the number of switching events,the higher the dynamic power consumption. The static component on the other hand ispresent even when no switching occurs and is caused by static conductive paths betweenthe supply rails or by leakage currents. It is always present, even when the circuit is instand-by. Minimization of this consumption source is a worthwhile goal.

The propagation delay and the power consumption of a gate are related—the propa-gation delay is mostly determined by the speed at which a given amount of energy can bestored on the gate capacitors. The faster the energy transfer (or the higher the power con-sumption), the faster the gate. For a given technology and gate topology, the product ofpower consumption and propagation delay is generally a constant. This product is calledthe power-delay product (or PDP) and can be considered as a quality measure for aswitching device. The PDP is simply the energy consumed by the gate per switchingevent. The ring oscillator is again the circuit of choice for measuring the PDP of a logicfamily.

An ideal gate is one that is fast, and consumes little energy. The energy-delay prod-uct (E-D) is a combined metric that brings those two elements together, and is often usedas the ultimate quality metric. From the above, it should be clear that the E-D is equivalentto power-delay2.

Example 1.7 Energy Dissipation of First-Order RC Network

Let us consider again the first-order RC network shown in Figure 1.21. When applying a stepinput (with Vin going from 0 to V), an amount of energy is provided by the signal source to thenetwork. The total energy delivered by the source (from the start of the transition to the end)can be readily computed:

(1.15)

It is interesting to observe that the energy needed to charge a capacitor from 0 to V voltwith a step input is a function of the size of the voltage step and the capacitance, but is inde-

Ppeak ipeak= Vsupply max p t( )[ ]=

Pav1T--- p t( )dt

0

T

∫Vsupply

T---------------- isupply t( )dt

0

T

∫= =

Ein iin t( )vin

0

∞

∫= t( )dt V Cdvout

dt------------dt

0

∞

∫ CV( ) dvout

0

V

∫ CV2= = =



Depending upon the design problem at hand, different dissipation measures have tobe considered. For instance, the peak power Ppeak is important when studying supply-linesizing. When addressing cooling or battery requirements, one is predominantly interestedin the average power dissipation Pav. Both measures are defined in equation Eq. (1.14):

(1.14)

where p(t) is the instantaneous power, isupply is the current being drawn from the supplyvoltage Vsupply over the interval t ∈ [0,T], and ipeak is the maximum value of isupply over thatinterval.

The dissipation can further be decomposed into static and dynamic components. Thelatter occurs only during transients, when the gate is switching. It is attributed to thecharging of capacitors and temporary current paths between the supply rails, and is, there-fore, proportional to the switching frequency: the higher the number of switching events,the higher the dynamic power consumption. The static component on the other hand ispresent even when no switching occurs and is caused by static conductive paths betweenthe supply rails or by leakage currents. It is always present, even when the circuit is instand-by. Minimization of this consumption source is a worthwhile goal.

The propagation delay and the power consumption of a gate are related—the propa-gation delay is mostly determined by the speed at which a given amount of energy can bestored on the gate capacitors. The faster the energy transfer (or the higher the power con-sumption), the faster the gate. For a given technology and gate topology, the product ofpower consumption and propagation delay is generally a constant. This product is calledthe power-delay product (or PDP) and can be considered as a quality measure for aswitching device. The PDP is simply the energy consumed by the gate per switchingevent. The ring oscillator is again the circuit of choice for measuring the PDP of a logicfamily.

An ideal gate is one that is fast, and consumes little energy. The energy-delay prod-uct (E-D) is a combined metric that brings those two elements together, and is often usedas the ultimate quality metric. From the above, it should be clear that the E-D is equivalentto power-delay2.

Example 1.7 Energy Dissipation of First-Order RC Network

Let us consider again the first-order RC network shown in Figure 1.21. When applying a stepinput (with Vin going from 0 to V), an amount of energy is provided by the signal source to thenetwork. The total energy delivered by the source (from the start of the transition to the end)can be readily computed:

(1.15)

It is interesting to observe that the energy needed to charge a capacitor from 0 to V voltwith a step input is a function of the size of the voltage step and the capacitance, but is inde-

Ppeak ipeak= Vsupply max p t( )[ ]=

Pav1T--- p t( )dt

0

T

∫Vsupply

T---------------- isupply t( )dt

0

T

∫= =

Ein iin t( )vin

0

∞

∫= t( )dt V Cdvout

dt------------dt

0

∞

∫ CV( ) dvout

0

V

∫ CV2= = =


CAPACITÂNCIASq A capacitância de um sinal é composta por:

§ capacitância de saída da porta lógica (DRENO/SOURCE)§ capacitância de roteamento§ somatório das capacitâncias de gate conectadas ao sinal

Cdreno/source

Cg1

Cg2

Cg3

Cg4

Croteamento

38

Capacitâncias parasitas

39

capac

itância

de saíd

a da

porta ló

gica (D

RENO/SOURCE)

capac

itância

de rotea

mento

somató

rio das

capac

itância

s

de gate

Roteamentoq A carga do roteamento deve ser acrescida ao CL na

equação do atraso das portas.q Hoje o atraso devido ao roteamento é da mesma

ordem de grandeza do atraso das portas lógicas.

2...7.0:

o)comprimentdeunidadeporcia(capacitân/

o)comprimentdeunidadeporia(resistênc/

2lcrtfionoatraso

mFc

mr

=

®

W®

µ

µ

wl

40

Roteamento

q linhas longas§ Supondo: r=20W/µm e c=0,4 fF/ µ m§ Atraso em uma linha de 1000 µ m

t = 0.35 . 20 . 0,4e-15 . (1000)2 = 2.8ns

§ Atraso em uma linha de 2000 µ mt = 0.35 . 20 . 0,4e-15 . (2000)2 = 11.2ns

§ Solução indicada para acelerar a linha de 2000 µm:

1000 µm (2.8ns) 1000 µm (2.8ns)tbuffer < 1ns

41

42

1

Fernando Moraes 17/Março/2020

1) Explicar na tabela abaixo a influência dos principais parâmetros do transistor MOS na corrente Ids

(corrente dreno-source).

Parâmetro Ação para aumentar o Ids (duas respostas possíveis: aumentar ou diminuir)

Explicar a razão

W aumentar Maior quantidade de portadores no canal L diminuir Maior distância para os portadores atravessarem

Mobilidade aumentar Maior quantidade no Dreno/Soure

Espessura óxido diminuir Aumenta capacitância – menor campo elétrico é necessário

2) Porque o parâmetro W do transistor P deve ser maior que o W do transistor N em um inversor para que o tempo de subida seja o mesmo que o tempo de descida? Devido à mobilidade do transistor P ser menor que a mobilidade do Transistor N

3) A figura abaixo ilustra a curva DC do inversor, para o caso que o dimensionamento Wp/Wn é

equivalente ao fator de mobilidade µn/µp (Wp/Wn = µn/µp).

Ponto NMOS PMOS

1 C L 2 S L 3 S S 4 L S 5 L C

Pede-se: a) Qual o estado dos transistores N e P para cada um dos 5 pontos da curva, completando a tabela acima com

as letras: C, L, S(cortado, linear (ou resistivo), saturado). b) Como ficaria esta curva DC no caso do dimensionamento Wp/Wn <µn/µp? Justifique, desenhando a nova

curva no mesmo gráfico acima. 4) Considere o inversor abaixo, com o W (width) dos transistores N e P iguais a 0,4 µm e 1,2 µm

respectivamente. A relação de mobilidade para a tecnologia é igual a 2. Qual a curva de transferência DC esperada para este inversor? Justifique.

Wp / Wn = 3 à Transistor P com maior ganho – curva move-se para a direita – slide 16

(4)

V(out)

V(in)

(1)

(2)

(3)

(5)

1

Fernando Moraes 17/Março/2020

1) Explicar na tabela abaixo a influência dos principais parâmetros do transistor MOS na corrente Ids

(corrente dreno-source).

Parâmetro Ação para aumentar o Ids (duas respostas possíveis: aumentar ou diminuir)

Explicar a razão

W aumentar Maior quantidade de portadores no canal L diminuir Maior distância para os portadores atravessarem

Mobilidade aumentar Maior quantidade no Dreno/Soure

Espessura óxido diminuir Aumenta capacitância – menor campo elétrico é necessário

2) Porque o parâmetro W do transistor P deve ser maior que o W do transistor N em um inversor para que o tempo de subida seja o mesmo que o tempo de descida? Devido à mobilidade do transistor P ser menor que a mobilidade do Transistor N

3) A figura abaixo ilustra a curva DC do inversor, para o caso que o dimensionamento Wp/Wn é

equivalente ao fator de mobilidade µn/µp (Wp/Wn = µn/µp).

Ponto NMOS PMOS

1 C L 2 S L 3 S S 4 L S 5 L C

Pede-se: a) Qual o estado dos transistores N e P para cada um dos 5 pontos da curva, completando a tabela acima com

as letras: C, L, S(cortado, linear (ou resistivo), saturado). b) Como ficaria esta curva DC no caso do dimensionamento Wp/Wn <µn/µp? Justifique, desenhando a nova

curva no mesmo gráfico acima. 4) Considere o inversor abaixo, com o W (width) dos transistores N e P iguais a 0,4 µm e 1,2 µm

respectivamente. A relação de mobilidade para a tecnologia é igual a 2. Qual a curva de transferência DC esperada para este inversor? Justifique.

Wp / Wn = 3 à Transistor P com maior ganho – curva move-se para a direita – slide 16

(4)

V(out)

V(in)

(1)

(2)

(3)

(5)

43

2

5) Explique porque em células CMOS estáticas deve haver dualidade nas conexões (série em uma plano

e paralelo no outro plano). Mostrar através de exemplos os problemas que podem ocorrer. 6) A figura abaixo ilustra um oscilador em anel.

Pede-se: (a) Dado que tr=1.0 ns (tempo de propagação de

subida de um inversor) e tf=0.5 ns (tempo de propagação de descida de um inversor), qual o período (unidade: ns) e a frequência (unidade: MHz) resultante no nodo S?

(b) A figura abaixo ilustra a saída do oscilador. Determine os tempos tA, tB, tC, tD, mostrando como os mesmos foram obtidos. Como os tempos de subida e descida são diferentes, o dutty cycle não é 50%.

7)

1 0,5 1 0,5 1 0,5 1 à 5,5 ns 0,5 1 0,5 1 0,5 1 0,5 à 5 ns T = 10,5 ns à f= 95,24 MHz

in

gnd

vcc

out

Wn = 0.4 µm

Wp = 1.2 µm

µnµp = 2 Vcc/2

Vcc/2

v(in)

v(out)

vcc

t (ns)

Sinal S

tA

vcc/2

tB tC tD0

S

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