pontos-flutuantes em System Verilog

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    module PontosFlutuantes( 

    input logic [31:0] A,B,input logic clk,

      output logic exception,  output logic [31:0] SumFloat);

    reg [23:0] mantA, mantB;reg [7:0] expA, expB, d;reg sinalA, sinalB;

    reg [24:0] sum_mant;

    logic exp_sum;

    integer i;

    logic bit_guarda, bit_arredond, stick_bit;

    always_comb beginmantA

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    //stick_bit