FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO

An Instrumentation Amplifier forMyoelectric Signals

Henrique Rodrigues de Castro Mendes Martins

PREPARAÇÃO DA DISSERTAÇÃO

PREPARAÇÃO DA DISSERTAÇÃO

Advisor: PhD:Vitor Grade Tavares

February 19, 2013

c© Henrique Rodrigues de Castro Mendes Martins, 2013

An Instrumentation Amplifier for Myoelectric Signals

Henrique Rodrigues de Castro Mendes Martins

PREPARAÇÃO DA DISSERTAÇÃO

February 19, 2013

Resumo

Nas décadas passadas, o setor da eletrónica evoluiu exponencialmente. No nosso dia a dia aeletrónica está presente em tudo, nos nossos carros, e até em algumas das nossas roupas. A verdadeé que os desenvolvimentos nesse setor aumentaram a qualidade de vida do Homem. No caso dealgumas doenças, apenas com o auxílio de sistemas eletrónicos é possível realizar diagnósticose tratamentos apropriados. Problemas do foro muscular e de movimento são uma vasta área naqual a eletrónica teve grande influência na ajuda a lidar e a tratar essas doenças. A eletrónicamoderna permite uma melhor visão do que se passa ao nivel do músculo. Com instrumentaçãode grande precisão é possivel obter o sinal gerado pelas fibras das membranas musculares, o sinalmiográfico. Os sinais miográficos são signais muito específicos; eles são formados por variaçõesfisiológicas nas fibras das membranas musculares. A medição e o processamento destes sinais é degrande importância, dado que eles permitem olhar diretamente para o músculo. Isto é uma análiseimportante que precisa de ser feita para :

• Ajudar na tomada de decisão antes/após da cirurgia;

• Permitir a medição do desempenho muscular;

• Ajudar no processo de reabilitação;

Estes são apenas alguns exemplos daquilo que é possível atingir investindo na investigaçãoe desenvolvimento de sistemas aplicados a esta área em específico. Com isso em mente, a ne-cessidade de um sistema que meça e processe tais sinais surge. O objetivo desta tese é então dedesenvolver uma parte desse sistema, um amplificador de instrumentação de baixo ruído e de baixapotência para ser integrado em chip, usando a tecnologia CMOS de 0.35 µm. Este amplificadordeve seguir um conjunto de regras, dado que este tipo de sinais requerem caraterísticas muito es-pecíficas no amplificador e no processamento de sinal, nomeadamente um CMRR(Common-moderejection ratio) elevado, baixo ruído e baixo consumo de potência, dado que o chip a ser produzidoserá usado em aplicações de elevada autonomia. É então esperado atingir no fim desta tese um am-plificador genérico para sinais de baixa tensão e frequência:caraterísticas estas que estão presentena maior parte dos sinais biológicos.

i

ii

Abstract

In the past decades, the electronics sector has evolved exponentially. In our everyday there iselectronics everywhere, in our cars, in our houses and even in some of our clothes. Truth is, thedevelopments in that sector have increased the quality of life of the average Man. In the caseof some diseases, only with the aid of electronic systems proper diagnosis and treatments canbe made. Muscular and movement related problems are a wide area in which electronics have agreat influence in dealing with such diseases. Modern electronics allows us to take a better lookat what is going on at the muscle level. With great precision instrumentation we can obtain thesignal generated by muscle fiber membranes, the Myographic signal. Myographic signals are avery specific type of signals; they are formed by physiological variations in the state of musclefibre membranes [1]. The measuring and processing of these signals is of great importance, sincethey allow looking directly into the muscle [1]. This is an important analysis that needs to be doneto:

• Help in decision making both before/after surgery;

• Allow measurement of muscular performance;

• Aid in the rehabilitation process;

These are just a few examples of what we can achieve investing in the research and develop-ment of electronic systems applied to this specific area. With that in mind, the need for a systemthat can measure and process such signals arises. The goal of this thesis is to develop a part of thatsystem, an instrumentation amplifier to be integrated on chip, using CMOS 0.35 µm technology.This amplifier must follow a set of rules, since these signals demand very specific characteristicson an amplifier and in the signal processing, such as a good CMRR (Common-mode RejectionRatio), low noise and low power consumption, as this chip is to be used on high autonomy appli-cations. Thus, it is hoped to achieve in the end of this thesis a generic amplifier for low voltageand low frequency signals: characteristics that are present in most of the biological signals.

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Contents

1 Introduction 11.1 Document structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Theoretical Background 32.1 Myoelectric signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1.1 What are they? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1.2 Obtaining and measuring . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2.1 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2.2 Flicker Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2.3 Noise in Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3.1 Basic transistor configurations . . . . . . . . . . . . . . . . . . . . . . . 62.3.2 Single Stage Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3.3 Differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.3.4 Differential pair with load resistors . . . . . . . . . . . . . . . . . . . . 112.3.5 Common-mode Response . . . . . . . . . . . . . . . . . . . . . . . . . 122.3.6 CMOS Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . 132.3.7 Stability and Frequency Compensation . . . . . . . . . . . . . . . . . . 172.3.8 Common-mode Feedback . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.9 Class Type of Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Bybliographic Review 253.1 A CMOS Fully Balanced Differential Difference Amplifier and Its Applications [2] 253.2 A New Architecture for Rail-to-Rail Input Constant-gm CMOS Operational Transcon-

ductance Amplifiers [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.3 A 1 Volt CMOS Pseudo Differential Amplifier [4] . . . . . . . . . . . . . . . . 293.4 Low-Voltage Rail-to-Rail CMOS Differential Difference Amplifier [5] . . . . . 313.5 A CMOS Chopper-Stabilized Differential Difference Amplifier for Biomedical

Integrated Circuits [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.6 System design of a low noise, low offset instrumentation amplifier with chopper

stabilization [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4 Problem Presentation 354.1 Preliminary topology for an instrumentation amplifier . . . . . . . . . . . . . . . 35

5 Methodology and Work Plan 37

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vi CONTENTS

List of Figures

2.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 Differential pair modelled with noise sources . . . . . . . . . . . . . . . . . . . 52.3 Common-source topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4 Common-source with source resistor topology . . . . . . . . . . . . . . . . . . . 72.5 Common-source with capacitor topology . . . . . . . . . . . . . . . . . . . . . . 72.6 Source-Follower topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.7 Common-gate topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.8 Nmos amplifier with an enhancement load . . . . . . . . . . . . . . . . . . . . . 92.9 Nmos amplifier with a Depletion load . . . . . . . . . . . . . . . . . . . . . . . 102.10 Nmos amplifier with a Pmos load . . . . . . . . . . . . . . . . . . . . . . . . . . 102.11 Basic Differential pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.12 Basic Differential pair with common mode input . . . . . . . . . . . . . . . . . 122.13 Basic Differential pair with CMOS active load . . . . . . . . . . . . . . . . . . . 132.14 Differential pair with cascoding . . . . . . . . . . . . . . . . . . . . . . . . . . 142.15 Differential pair with current source load . . . . . . . . . . . . . . . . . . . . . . 142.16 Differential pair equivalent half circuit . . . . . . . . . . . . . . . . . . . . . . . 152.17 Differential pair with current source load . . . . . . . . . . . . . . . . . . . . . . 162.18 Differential pair with mirror pole representation . . . . . . . . . . . . . . . . . . 172.19 Two-stage operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 182.20 Differential pair with inputs shorted to outputs . . . . . . . . . . . . . . . . . . . 192.21 Common-mode feedback with resistive sensing . . . . . . . . . . . . . . . . . . 202.22 Common-mode feedback with source followers . . . . . . . . . . . . . . . . . . 212.23 Common-mode feedback with MOSFETs operating in deep triode region . . . . 212.24 Sensing and controlling the output CM level . . . . . . . . . . . . . . . . . . . . 22

3.1 Differential Difference Amplifier. Image obtained from [2] . . . . . . . . . . . . 253.2 Differential Difference Amplifier - Implementation. Image obtained from [2] . . 263.3 Fully Balanced Differential Difference Amplifier - Implementation. Image ob-

tained from [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.4 A simple rail to rail input stage. Image obtained from [3] . . . . . . . . . . . . . 283.5 New constant gm rail-to-rail input stage. Image obtained from [3] . . . . . . . . 283.6 Conventional method for biasing the current summation circuit. Image obtained

from [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.7 Diagram block of the pseudo-differential amplifier. Image obtained from: [4] . . 303.8 Diagram block of the pseudo-differential amplifier. Image obtained from: [4] . . 303.9 Maximum current selecting circuit. Image obtained from: [5] . . . . . . . . . . 313.10 rail-to-rail V-I converter. Image obtained from: [5] . . . . . . . . . . . . . . . . 323.11 Circuit Diagram of the CHSDDA. Image obtained from: [6] . . . . . . . . . . . 33

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viii LIST OF FIGURES

3.12 Rail-to-rail input pre amplifier. Image obtained from: [7] . . . . . . . . . . . . . 34

4.1 Initial amplifier proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1 Gant chart of the work plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

List of Tables

2.1 A comparison table between basic transistor configurations . . . . . . . . . . . . 9

ix

x LIST OF TABLES

Abbreviations and symbols

BPF Band-Pass FilterCHSDDA Chopper Stabilized Differential Difference AmplifierCM Common-modeCMFB Common-mode FeedbackCMOS Complementary Metal-Oxide-SemiconductorCMRR Common-mode Rejection RatioDDA Differential Difference AmplifierEEG ElectroencephalogramEMG ElectromyographicFDDA Fully Differential Difference AmplifierFBDDA Fully Balanced Differential Difference AmplifierLPF Low-Pass FilterMOSFET Metal Oxide Semiconductor Field Effect TransistorNMOS nFET Metal Oxide SiliconOTA Operational Transconductance AmplifierPD Pseudo DifferentialPDA Pseudo Differential AmplifierPMOS pFET Metal Oxide SiliconRF Radio Frequency

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Chapter 1

Introduction

The system responsible for the measuring and processing of myoelectric signals consists of elec-

trodes, an instrumentation amplifier, a filter, a sample and hold circuit and an analog to digital

converter (ADC). Electrodes are an important part of the system, as they allow us to measure the

Myographic signals, when strategically positioned on the patient’s skin. Since the characteristics

of these signals are far from optimal for one to properly process them, the use of the instrumen-

tation amplifier is justified. It will bring the signal to a band of voltage that will permit us to

handle these signals with no additional efforts. However, precautions must be taken in the devel-

opment and building of the instrumentation amplifier, to assure there are no external components

interfering with the signal, such as noise. The goal of this thesis is to develop a new instrumenta-

tion amplifier topology, based on the CMOS 0,35 µm technology, simulate its operation and then

implement it in an integrated circuit.

1.1 Document structure

The document is organized in the following chapters:

• Chapter 2 - Provides the necessary theoretical background regarding Myographic signals,

noise and differential amplifiers. Differential amplifiers will be thoroughly explained.

• Chapter 3 – Some amplifier topologies are presented, as well as a discussion about the

comparison of them.

• Chapter 4 – A preliminary solution is presented.

• Chapter 5 - A methodology for the project is made.

1

2 Introduction

Chapter 2

Theoretical Background

The purpose of this chapter is to enlighten the reader, providing the necessary theoretical back-

ground for him to read the document with clear understanding of what is the topic of discussion.

2.1 Myoelectric signals

2.1.1 What are they?

A myoelectric signal, also called a motor action potential, is an electrical impulse that produces

contraction of muscle fibers in the body. The term is most often used in reference to skeletal

muscles that control voluntary movements. Myoelectric signals have frequencies ranging from a

few hertz to about 300 Hz, and voltages ranging from microvolts to milivolts.

2.1.2 Obtaining and measuring

Myoelectric signals are detected by placing three electrodes on the skin. Two electrodes are posi-

tioned so there is a voltage between them when a myoelectric signal occurs. The third electrode

is placed in a neutral area, and its output is used to cancel the noise that can otherwise inter-

fere with the signals from the other two electrodes. The output voltage is processed using the

differential amplifier. The output of the amplifier has much higher voltage than the myoelectric

signals themselves. This higher voltage, which produces significant current, can be used to control

electromechanical or electronic devices.

2.1.3 Applications

Myoelectric signals are of interest to the developers of prosthetic devices, such as artificial limbs.

The signals can also be used to facilitate the operation of a computer using small voluntary muscle

movements, such as blinking the eyelids. Figure 2.1 contains a summary of applications for

electromyography (EMG).

3

4 Theoretical Background

Figure 2.1: Applications

2.2 Noise

Noise limits the minimum signal level that a circuit can process with acceptable quality. Analog

designers must take into consideration noise when designing circuits, because it trades with power

dissipation, speed and linearity. In this type of systems, the kinds of noise we have to take into

account are thermal noise, and flicker noise, also known as 1/f noise. Noise is a random process,

i.e. we cannot predict any values of noise. To incorporate noise in analog circuits a statistical

model is done, observing its behaviour for a long time. This allows us to determine some important

characteristics of noise, such as average power. The average power is: Pav = limT→+∞1T

∫ T/2−T/2 v2 dt

In circuits we can easily obtain the power expressed by W, when that same voltage is applied

to a load R, the power is defined as Pav/R. The concept of average power becomes more versatile

if defined with regard to the frequency content of noise. The power spectral density spectrum (

Sx(f) ) shows how much power the signal carries at each frequency, and it is defined as the average

power carried by x(t) in a one-hertz bandwidth around the frequency f .

2.2.1 Thermal Noise

Resistor thermal noise – The random motion of electrons in a conductor introduces fluctuations in

the voltage measured across the conductor even if the average current is zero. Thus, the spectrum

of thermal noise is proportional to the absolute temperature: Sv( f ) = 4kT R, f ≥ 0 Where k is the

Boltzmann constant. MOS thermal noise – MOS transistors also exhibit thermal noise. The most

significant source is the noise generated in the channel. For a long-channel MOS device operating

in saturation, the channel noise can be modelled by a current source connected between the drain

and source terminals with a spectral density:

2.2 Noise 5

2.2.2 Flicker Noise

The interface between the gate oxide and the silicon substrate in a MOSFET entails an interesting

phenomenon. Since the silicon crystal reaches an end at this interface, many “dangling” bonds

appear, giving rise to extra energy states. As charge carriers move at the interface, some are ran-

domly trapped and later released by such energy states, introducing flicker noise in the drain. In

addition to trapping, several other mechanisms are believed to generate flicker noise [1]. The

average power of this type of noise cannot be predicted easily, unlike the thermal kind. Depending

on the oxide-silicon interface characteristics, flicker noise may assume considerably different val-

ues and as such varies from one CMOS technology to another. It is modelled as a voltage source

in series with the gate and given by the following equation:

V 2n =

KCoxWL

.1f

(2.1)

Where K is a process dependent constant on the order of 10−23. The trap-and-release phe-

nomenon associated with the dangling bonds occurs at low frequencies, since the noise spectral

density is inversely proportional to frequency. This is the reason why this type of noise is also

known as 1/f noise. Since the signals to be measured have low frequencies, this noise must be

taken into account, upon the developing of the amplifier.

2.2.3 Noise in Differential Pairs

Figure 2.2 shows a differential pair with the overall noise modelled.

Figure 2.2: Differential pair modelled with noise sources

6 Theoretical Background

We can obtain the input-referred noise voltage by taking into account the output noise of M3

and M4. The drain noise current of M3 is divided between ro3 and the resistance seen looking

into the drain of M1. This resistance RX = ro4 + 2ro1. Denoting the resulting noise currents

flowing through ro3 and RX by InA and InB, respectively , we have: InA = gm3Vn3(ro4+2ro1)(2ro4+2ro1)

and

InB = gm3Vn3ro3

(2ro4+2ro1). The former produces a noise voltage gm3Vn3ro3

(ro4+2ro1)(2ro4+2ro1)

at node X with

respect to ground, whereas the latter flows through M1, M2 and ro4, generating gm3Vn3(ro3ro4)

(2ro4+2ro1)

at node Y, with respect to ground. Thus, the total differential output noise due to M3 is equal to

gm3Vn3(ro3ro1)(ro3+ro1)

. We can conclude then, that the noise current of M3 is simply multiplied by the

parallel combination of ro1 and ro3 to produce the differential output voltage.

2.3 Amplifiers

The purpose of this chapter is to enlighten the reader in the analog electronics design fields, namely

amplifiers. The reader can find more information about amplifiers here: [8], [9].

2.3.1 Basic transistor configurations

2.3.1.1 Common-source configuration

This configuration is normally used in the gain stage, since it can achieve a high gain value.

Figure 2.3: Common-source topology

Transistor kept in saturation through R1 and R2.

Open loop gain Av =Vo/Vi =−gmVgsRi(ro//Rd)(Ri+Rsi)

Input resistor Ri = R1/R2

Output resistor Ro = Rd//ro

With source resistor

2.3 Amplifiers 7

Figure 2.4: Common-source with source resistor topology

Used to stabilize the quiescent point against variations of the parameters of the transistor.

However, the gain is reduced.

Open loop gain Av =− gmRd(1+gmRs)

With a bypass capacitor on the source

Figure 2.5: Common-source with capacitor topology

To minimize the loss of gain (because of Rs).

The stability of the quiescent point can be enhanced by replacing Rs with a current source.

Input pole: ωin =1

([Cgd(1+gmRD)+Cgs](RS))

Output pole: ωout =1

([RD||((Cgd+Cgs)

Cgd. 1

gm)](Ceq+Cdb)))

with Ceq = (CgdCgs)/(Cgd +Cgs)

2.3.1.2 Source-follower configuration

This configuration is normally used in the output stage of an amplifier, because of its low output

resistor.

8 Theoretical Background

Figure 2.6: Source-Follower topology

Open loop gain Av =Vo/Vi =(Rs//ro)Ri

((1/gm+Rs//ro).(Ri+Rsi))

Input resistor Ri = R1/R2

Output resistor Ro = 1/gm//Rs//ro

Significant pole: ωp =gm

([(gmRD)+Cgs](RS))

2.3.1.3 Common-gate configuration

This configuration is much less used, standing alone, than source follower, or common source.

It is usually used in CMOS RF receivers or in cascode configurations. The transistor is kept in

saturation by the current source.

Figure 2.7: Common-gate topology

Open loop gain Av =Vo/Vi = gm(Rd//RL)

Input resistor Ri = 1/gm

Output resistor Ro = Rd

To better understand the differences between these configurations, a comparison table is presented:

2.3 Amplifiers 9

Table 2.1: A comparison table between basic transistor configurations

Topology Av Ai Ri Ro

Common-Source Av > 1 - Rth Moderate to highSource-Follower Av ∼= 1 - Rth LowCommon-Gate Av > 1 Ai ∼= 1 Low Moderate to high

2.3.2 Single Stage Amplifiers

These are the basic MOS load topologies:

• NMOS with enhancement load

• NMOS with depletion load

• NMOS amplifier with PMOS load

The last one is one of the most used active load configurations, for example it is used in the

differential pair.

NMOS with enhancement load

Figure 2.8: Nmos amplifier with an enhancement load

Open loop gain Av =−gmD/gmL

NMOS with depletion load

10 Theoretical Background

Figure 2.9: Nmos amplifier with a Depletion load

Av =−gmD(roD//roL)

NMOS amplifier with PMOS load

Figure 2.10: Nmos amplifier with a Pmos load

Av =−gmn(ron//rop)

2.3.3 Differential amplifiers

This section deals with one of the most used input stages, the differential pair. Because of its

useful characteristics, it is the dominant choice in today’s high performance analog and mixed

signal circuits. So, what makes us choose differential over single ended operation?

• Environmental noise immunity

• Increase in the maximum achievable voltage swings

• Simpler biasing

2.3 Amplifiers 11

• Higher linearity

Although differential operation brings a lot of benefits, it has a small drawback: the occupied

area. This section enlightens the reader on the basic differential pair, a detailed analysis on its

mode of operation, and possible negative feedback topologies, as well as common mode feedback

topologies.

2.3.4 Differential pair with load resistors

Figure 2.11: Basic Differential pair

To allow normal operation, it is imperative to ensure that both M1 and M2 stay in saturation. Their

mode of operation can move to the triode area if there is a disturbance in the common mode level,

affecting their currents. Thus it is important that the bias currents of the devices have minimal

dependence on the input CM level. To do that a current source is used.

If the input voltage swing increases (Vin1−Vin2), the circuit becomes more non-linear, due to

one of the transistors absorbing all of ISS (in the worst case scenario), and the other one absorbs

none, thus one of them goes into cut-off and the other remains in saturation. Therefore its max-

imum and minimum voltage output varies from VDD and VDD−RDISS. For Vin1 = Vin2 the circuit

is in equilibrium. The range of the minimum and maximum common mode voltage can also be

obtained: M1 and M2 enter the triode region if Vin,CM > Vout1 +Vth = VDD−RDISS/2+Vth, and

if Vin,CM > Vgs1 +Vgs3−Vth we guarantee that both M1 and M2 remain in saturation. Thus we

set limits for Vin,CM : Vgs1 +Vgs3−Vth ≤ Vin,CM ≤ min(VDD−RDISS/2+Vth,VDD) . Now that the

common mode voltage is defined, we can define the maximum values for the output voltage: it

can go as high as VDD, and as low as approximately Vin,CM−Vth.

12 Theoretical Background

2.3.5 Common-mode Response

Figure 2.12: Basic Differential pair with common mode input

One of the most important attributes of differential amplifiers is their ability to suppress the effect

of common mode perturbations. In reality, neither the circuit is fully symmetric, nor does the

current source exhibits infinite output impedance. By definition AV,CM = VoutVin,CM

= − (RD/2)(1/(2gm)+RSS)

.

If the resistor of the current source was of infinite value, AV,CM would be zero. The finite output

impedance of the tail current source results in some common-mode gain in a symmetric differential

pair, as seen from the equation. This conclusion was made assuming the circuit was perfectly

symmetrical, but what if it wasn’t? Assuming there is a mismatch in a resistor, RD1 = RD1 +∆,

what happens to Vout1 and Vout2 as Vin,CM increases? Assuming M1 and M2 are symmetrical we

obtain: ∆Vout1 =−∆Vin,CMgm

(1+2gmRSS)(RD1+∆) and ∆Vout2 =−∆Vin,CMgm

(1+2gmRSS)(RD2), thus, a common mode change

at the input introduces a differential component at the output. This is a problem because if the input

of the differential pair includes both a differential signal and common mode noise, the circuit

corrupts the amplified differential signal by the input CM change. In conclusion, the common

mode response of differential pairs depends on the output impedance of the tail current source and

the asymmetries in the circuit.

2.3 Amplifiers 13

2.3.6 CMOS Differential Pair

Figure 2.13: Basic Differential pair with CMOS active load

In this case the load is done through an active load (diode connected or current-source load).

The small signal gain is: AV = gmN(ron||rop). The diode connected loads consume voltage head-

room, thus creating a trade-off between the output voltage swings, the voltage gain, and the input

common mode range. There are a lot of techniques that can be used to improve some of the char-

acteristics of this topology. For example, using current-source loads( 2.15) can help reduce the gm

of the diode connected load devices, by aiding in supplying the bias current, thus reducing their

currents rather than their aspect ratios, which will help increase the differential gain. However,

the small signal gain of the differential pair with current-source loads is relatively low; One way

to solve this problem is to increase the NMOS and PMOS output impedance through means of

cascoding ( 2.14). This method increases differential gain, but its drawback is an increase in the

consumption of more voltage headroom.

14 Theoretical Background

Figure 2.14: Differential pair with cascoding

Figure 2.15: Differential pair with current source load

2.3.6.1 Frequency Response

This section deals with the analysis of the frequency response of the differential pair, both for

differential signals and common mode signals.

2.3 Amplifiers 15

Figure 2.16: Differential pair equivalent half circuit

As we can see in figure Figure 2.16, its frequency response is similar to that of a common

source stage, exhibiting miller multiplication of Cgd . In this case both +Vin2/2and−Vin2/2 are

multiplied by the same transfer function, that brings us to the conclusion that the number of poles

in Vout/Vin is equal to that of each path (rather than the sum of the number of the poles in the two

paths). For common-mode signals, the high frequency gain is determined by the capacitance at

node P, which consists of Cgd3,Cdb3,Csb1 and Csb2. If M1-M3 are wide transistors this capacitance

will be of considerable value. Assuming there is a mismatch between M1 and M2,we can obtain

the common mode high frequency gain simply by replacing in the formula the drain resistor and

the output resistor of M3 with its own value in parallel with the capacitance seen through that node.

AV,CM =−(∆gm(RD||( 1

(CLs) )))

((gm1+gm2)[ro3||( 1(CPs)+1)

). This suggest that, if the output pole is much farther from the

origin than is the pole at node P, the common mode rejection of the circuit degrades considerably

at high frequencies. For differential pairs with high impedance loads made with active loads, an

analysis can be made for differential and common mode signals separately.

16 Theoretical Background

Figure 2.17: Differential pair with current source load

In this case, G is an ac ground, because Cgd3 and Cgd4 conduct equal and opposite currents to

that node. As we have a very high load seen from the output (ro3||(ro1), the dominant pole is given

by ((ro3||ro1)CL)(−1). The common mode behaviour of this circuit is similar to the one analysed

before. Let us consider now a differential pair with an active current mirror.

2.3 Amplifiers 17

Figure 2.18: Differential pair with mirror pole representation

In contrast to the fully differential configuration, this topology does not have the same transfer

function on both sides. The path consisting of M3 and M4 includes a pole at node E, which

is known as the mirror pole. This pole is greater in magnitude than the output pole, and it is

given by Cgs3,Cgs4,Cdb3,Cdb1 ,and the miller effect of Cgd1 and Cgd4. Even if only Cgs3 and Cgs4

are considered, the severe trade-off between gm(1/gm3) is the impedance seen through that node)

and Cgs of PMOS devices results in a pole that greatly impacts the performance of the circuit.

Through some abbreviations, the poles of this circuit are as follows: ωp1 = 1/(CL(roN ||roP)) and

ωp2 = gmP/CE where CE is the total capacitance at node E. There can also be obtained a zero in

the left half plane, and its value is 2ωp2. In summary, fully differential circuits do not possess a

mirror pole, another advantage against single ended circuits.

2.3.7 Stability and Frequency Compensation

Stability and frequency compensation is a topic that has to be taken into account by analog cir-

cuit designers. If we want to achieve higher output voltage swings, then a two stage operational

amplifier is required, and the study of such amplifier’s stability is of great importance.

18 Theoretical Background

Figure 2.19: Two-stage operational amplifier

Observing figure 2.19, we can identify 3 poles, one at A1(A2), another at B1(B2) and another

at X(Y ). As stated in the previous section the pole at X lies in the high frequencies. Since the small

signal resistance seen at A1 is high, even the capacitances of M3,M5 and M9 can create a pole

close to the origin.In the output, the resistance can be small, however, CL can be high, making the

circuit exhibit two dominant poles. A bode plot of this circuit can be found in [9]. Since the poles

at A1 and B1 are relatively close to the origin, the phase approaches −180o well below the third

pole. This implies that the phase margin may be close to zero even before the third pole contributes

with its phase shift. So, how do we compensate this circuit? The goal is to move a dominant pole

towards the origin so as to place the gain crossover well below the phase crossover. However,

the unity gain bandwidth after compensation cannot exceed the frequency of the second pole of

the open-loop system. Thus, the magnitude of ωp,A1 must be reduced, however, the available

bandwidth will be limited to approximately ωp,A1, which is a low value. Furthermore, the small

magnitude of the required dominant pole translates to a very large compensation capacitor, which

is not desired. In [9], a better approach is taken, also known as miller compensation, that creates

a large capacitance at node A1, and moves the output pole away from the origin.

2.3.8 Common-mode Feedback

As we have seen in the previous sections, fully differential amplifiers have many advantages in

comparison with their single ended counterparts, such as greater output swings, avoiding mirror

poles, thus achieving a higher closed loop speed. However, high gain differential circuits require

common-mode feedback. For a better understanding of the need of this type of feedback, an

example is required. In a differential amplifier, sometimes negative feedback is required, and for

that, we short the inputs and the outputs of the circuit. The input and output common mode levels

are well defined in this case: VDD−RDISS/2. Now suppose the load resistors are replaced by

2.3 Amplifiers 19

PMOS current sources , so as to increase the differential voltage gain. Figure 2.20 represents this

example.

Figure 2.20: Differential pair with inputs shorted to outputs

What is the common mode level at the output node? Since each of the input transistors carry

half of the tail current, the CM level depends on how close the PMOS current values are to that

value. Suppose there is a mismatch in the PMOS and NMOS current mirrors defining an error

between their drain currents and ISS/2. If we assume the drain currents of both M3 and M4 in

the saturation region are slightly greater than ISS/2, both M3 and M4 must enter the triode region

so that their drain currents match ISS/2. Conversely, if their drain currents are inferior to ISS/2

then both Vout1 and Vout2 must drop so that M5 enters the triode region, thereby producing only

2ID3,4. The above difficulties arise because in high gain amplifiers, we want to use a p-type current

source to balance an n-type current source. The difference between the currents, IP and IN flows

through the intrinsic output impedance of the amplifier, creating an output voltage change equal

to (IP− In)(RP||Rn). Since the current error depends on mismatches and the load associated with

it is high, the voltage error can become very large, thus driving the n-type or p-type current source

into the triode region. It is emphasized that differential feedback cannot define the CM level. As

expected, in high gain amplifiers, the output CM level is quite sensitive to device properties and

mismatches and it cannot be stabilized by means of differential feedback. Thus, a common mode

feedback network must be added to sense the CM level of the two outputs and accordingly adjust

one of the bias currents in the amplifier. CMFB consists of three operations:

• Sensing the output CM level

20 Theoretical Background

• Comparison with a reference

• Returning the error to the amplifier’s bias network

Recalling that Vout,CM = (Vout1 +Vout2)/2, a resistive divider can be employed as shown in figure

2.21.

Figure 2.21: Common-mode feedback with resistive sensing

This generates a voltage Vout,CM = (R1Vout1+R2Vout2)(R1+R2)

, that is equal to (Vout1 +Vout2)/2 if the re-

sistors are equal. The difficulty here is that both resistors must be much greater than the output

impedance of the amplifier so as to avoid lowering the open loop gain. Such large resistors occupy

a very large area and suffer from substantial parasitic capacitance to the substrate. To eliminate

the resistive loading, we can interpose source followers between each output and its corresponding

resistor as seen in figure 2.22.

2.3 Amplifiers 21

Figure 2.22: Common-mode feedback with source followers

This technique produces a CM level that is in fact lower that the output CM level by the gate-

source voltage of transistors M7/M8. It is also important to state that R1 and R2 or I1 and I2 must

be large enough to ensure that M7 or M8 can handle a large differential swing on the output.

However, this sensing method has an important drawback: it limits the differential output swings

(even if the resistors and the currents are large enough) by approximately the threshold voltage.

Another type of CM sensing can be seen in figure 2.23:

Figure 2.23: Common-mode feedback with MOSFETs operating in deep triode region

In this type of sensing, we use two transistors in deep triode region, introducing a total

impedance that is equal to the parallel of M7 and M8 output resistors, which vary with the width,

22 Theoretical Background

the length of the transistors and Vout1 +Vout2. If both the outputs rise together, then the total load

imposed by the transistors will drop, whereas if they change differentially, the load of one transis-

tor will increase and the other will decrease. As the resistor-based sensing method, this method

also limits the output voltage swing. Now that we have a method of sensing the CM level, it is

imperative to compare it with a reference and return the difference to the bias network. To do

this, an op amp can be employed, connected to the NMOS current sources, as we can see in figure

2.24:

Figure 2.24: Sensing and controlling the output CM level

The mode of operation is as follows: if both the output voltages increase, so does VE , thus

increasing the drain currents of M9 and M10 and lowering the output CM level. It can also be

interpreted as a form of forcing the CM level of both the outputs to the value of the reference, if

the open loop gain is high. This type of feedback can be applied to the PMOS current sources

as well. In some cases, the feedback can be used to control only one tail current source, to allow

optimization of the settling behaviour. As we’ve seen, both M9 and M10 were fed by the error

coming from the op amp. This technique consists of using only one of them to receive the error,

whilst the other is biased at a constant current.

2.3.9 Class Type of Amplifiers

This section provides the reader with an insight about the possible classes of the amplifiers. In our

case, it is only pertinent to study the A class , the B class and the AB class. For more information

on amplifier class types the reader can find it here : [10].

2.3.9.1 Class A

This is the most linear of the classes, meaning the output signal is a truer representation of the

input. Here are the characteristics of the class:

• The output transistor conducts for the entire cycle of the input signal. In other words, they

reproduce the entire waveform in its entirety.

2.3 Amplifiers 23

• These amplifiers work at higher temperatures, as the transistors in the amplifier are on and

running at full power all the time.

• There are no conditions to turn the transistors on/off. That doesn’t mean that the amplifier

is never off or can never be turned off; it means the transistors doing the work inside the

amplifier have a constant flow of electricity through them, also known as bias.

• Class A is the most inefficient of all power amplifier designs, averaging only around 20%.

Because of these factors, Class A amplifiers are very inefficient: for every watt of output

power, they usually waste at least 4-5 watts as heat. Because of this, they run hotter than the other

class types, increasing somewhat the thermal noise of the devices. All this is due to the amplifier

constantly operating at full power. The upside is that these amplifiers are the most enjoyed of

all amplifiers. Since the transistor reproduces the entire waveform without ever cutting off, the

waveform is more linear; that is, it contains much lower levels of distortion.

2.3.9.2 Class B

In this amp, the positive and negative halves of the signal are dealt with by different parts of the

circuit. The output devices continually switch on and off. Class B operation has the following

characteristics:

• The input signal has to be a lot larger in order to drive the transistor appropriately.

• This is almost the opposite of Class A operation.

• There has to be at least two output devices with this type of amplifier. The output stage

employs two output devices so that each side amplifies each half of the waveform. Either

both output devices are never allowed to be on at the same time, or the bias for each device

is set so that the current flowing in one output device is zero when not presented with an

input signal.

• Each output device is on for exactly one half of a complete signal cycle.

These amps run cooler than Class A amps, but the sound quality is not as pure, as there is a

lot of "crossover" distortion, as one output device turns off and the other turns on over each signal

cycle.

This type of amplifier design, or topology, gives us the term "push-pull," as this describes the

tandem of output devices that deliver the audio signal to your speakers: one device pushes the

signal, the other pulls the signal. They can be less expensive, because one can use two cheap

output devices instead of one high-quality one in the design.

As mentioned before, the input signal has to be lot a larger, meaning that from the amplifier

input, it needs to be "stepped up" in a gain stage, so that the signal will allow the output transistors

to operate more efficiently within their designed specifications. This means more circuitry in the

24 Theoretical Background

path of your signal, degrading sound even before it gets to the output stage. The efficiency of such

topology wanders around the 60 per cent, and its linearity is inferior to that of class A, as there is

a trade-off between efficiency and linearity.

2.3.9.3 Class AB

This is the compromise between both classes, A and B. Class AB operation has some of the best

advantages of both Class A and Class B built-in. Its main benefits are sound quality(linearity)

comparable to that of Class A and efficiency similar to that of Class B. Most modern amp designs

employ this topology.

Its main characteristics are:

• In fact, many Class AB amps operate in Class A at lower output levels, again giving the best

of both worlds

• The output bias is set so that current flows in a specific output device for more than a half

the signal cycle but less than the entire cycle.

• There is enough current flowing through each device to keep it operating so they respond

instantly to input voltage demands.

• In the push-pull output stage, there is some overlap as each output device assists the other

during the short transition, or crossover period from the positive to the negative half of the

signal.

There are many implementations of the Class AB design. A benefit is that the inherent non-

linearity of Class B designs is almost totally eliminated, while avoiding the heat-generating and

wasteful inefficiencies of the Class A design. And as stated before, at some output levels, Class

AB amps operate in Class A. It is this combination of good efficiency (around 50) with excellent

linearity that makes class AB the most popular audio amplifier design.

Chapter 3

Bybliographic Review

This chapter has the intent to provide the reader with the technological trends on instrumenta-

tion amplifiers until 2013. An explanatory and critical approach is taken when addressing every

relevant article.

3.1 A CMOS Fully Balanced Differential Difference Amplifier andIts Applications [2]

In this article, the authors wish to achieve a wide input range FBDDA(Fully balanced differential

difference amplifier) with low power consumption. It begins with an explanation about the DDA,

and the equations by which it operates:

Figure 3.1: Differential Difference Amplifier. Image obtained from [2]

Vo = Ao[(Vpp−Vpn)− (Vnp−Vnn)] Vpp−Vpn = Vnp−Vnn as Ao− > ∞ With these equations,

the conclusion is made that the open loop gain must be made as high as possible, so as to have

the differences between the input voltages close to zero. The amplifier presented next, has two

stages: a differential input – single ended output transconductance stage(differential pair with

active loads), and a second gain stage(common-source amplifier with active load). Next it is

described the input noise formulas, for both flicker and thermal noise:

V 2thermal =

323 kT ( 1

gmn)+ 16

3 kT ( gmngmp

2( 1gmp

))

25

26 Bybliographic Review

From which it is concluded that increasing the width of the input transistors diminish the 1/f

noise, as well as increasing their gmn. The proposed topology by the authors is presented in figure

3.2.

Figure 3.2: Differential Difference Amplifier - Implementation. Image obtained from [2]

The small-signal no-load gain of the DDA can approximately be expressed by: Ao = gmn(rds1||rds3||rds5)(gm9+

gm10)(rds9||rds10) Clearly the gain is proportional to gmn. Because of the virtual short property in

op-amps where the differential pair operates at Vd = 0, it is possible to select the width (W) of

the differential pair transistors as large as desired to increase its transconductance gm = for-

mula. Hence, noise is minimized and linearity is improved. [2]. Then, it is presented that there

is a trade-off between achieving high input differential range, low noise and low distortion in the

DDA designs. After introducing the DDA, a FBDDA architecture is proposed, along with its

CMFB(common-mode feedback) network. The CM output voltage is employed with 2 capacitors

and resistors. Two similar AB rail to rail output stages are employed to achieve low power con-

sumption with good output current driving capability. The FBDDA along with its CMFB network

is presented in figure 3.3:

3.2 A New Architecture for Rail-to-Rail Input Constant-gm CMOS OperationalTransconductance Amplifiers [3] 27

Figure 3.3: Fully Balanced Differential Difference Amplifier - Implementation. Image obtainedfrom [2]

The reader can find more information about DDAs here: [11], [12], [13], [14] and [15].

3.2 A New Architecture for Rail-to-Rail Input Constant-gm CMOSOperational Transconductance Amplifiers [3]

In this article, the authors present a new architecture for constant-gm rail-to-rail (R-R) input stages

that has less than 5 per cent deviation in gm over the entire range of the input common-mode

voltage. The topology presented here is of a folded cascode type, based on a floating current

source. Referring about the trade-off between speed, gain and power that exists at high voltage

supplies, the authors introduce the signal swing at the low voltage supplies, as another metric to

take into account. It is pertinent to refer that this swing is relative to the input swing, because the

output swing can be close to the power supply, using a class A or class AB output stage or even a

folded cascode architecture. To build a rail-to-rail input common mode range, two complementary

differential input stages are used, that deal with the extreme input voltages by using only one input

pair, with a total effective transconductance reduced by half. Therefore, the deviations in gmT as a

function of the input common mode voltage, VCM, can be as much as 100 per cent [3]. However,

in normal operation its input transconductance is the sum of the NMOS and the PMOS input stage

transconductance.

28 Bybliographic Review

Figure 3.4: A simple rail to rail input stage. Image obtained from [3]

Then it is presented the author’s topology, with the final goal of achieving a constant input gm

independently of the input’s voltage.

Figure 3.5: New constant gm rail-to-rail input stage. Image obtained from [3]

3.3 A 1 Volt CMOS Pseudo Differential Amplifier [4] 29

The principle of this new technique is to activate another pair similar to the active pair when

one pair has lost required gate bias for proper operation. As a result, at extreme supply voltage

ranges that one of input pairs turns off, two similar pairs of other polarity generate signal current

in parallel, and so the input transconductance doubles [3]. The circuit for the summation of the

currents can be seen in figure 3.6.

Figure 3.6: Conventional method for biasing the current summation circuit. Image obtained from[3]

The explanation of the functioning of the global circuit can be found here: [3].

The performance achieved by employing these architectures is enhanced, as well as obtaining

a low power, high swing, high speed and a high gain single-stage OTA(Operational transconduc-

tance amplifier).

3.3 A 1 Volt CMOS Pseudo Differential Amplifier [4]

This article presents a 1 V pseudo differential amplifier with a simple rail-to-rail CMFB circuit,

that consists in the traditional common-mode detector and the transimpedance and transconduc-

tance amplifiers. At first some advantages of using a pseudo-differential topology are presented,

such as allowing wider input and output ranges, and making the architecture much more attractive

to low power supplies. However, PD structure requires an extra common-mode feedback (CMFB)

circuit which serves two purposes: 1) to fix the common-mode voltage at high impedance nodes

30 Bybliographic Review

and 2) to suppress the common-mode signal components [4]. The proposed topology is presented

in figure 3.7, in the block diagram form.

Figure 3.7: Diagram block of the pseudo-differential amplifier. Image obtained from: [4]

When the outputs from GM(IN) are differential signals, the currents through resistors R are of

the same value but of opposite phase. These currents will flow to each resistor and they will be

imposed on OutlA and OutIB. Because these currents are of the same amplitude but opposite in

phase, there will be no input current to the transimpedance amplifier and no voltage variation at

node C. The current that flows through resistor R is also mirrored and positively fed back to the

output of the input transconductor GM(IN). As a result, the output impedance of the PDA(Pseudo

differential amplifier) at node Vo1 and Vo2 are given by Zout . When the outputs from the PDA are

common mode signals, the common mode current will flow through nodes A and B with the same

magnitude and phase. As a result, the summation of these two currents is passed to the common

mode amplifier (A) which consists of a transimpedance amplifier and an output transconductor

GMO. The output current of GMO is fed back to the output node of input transconductor GM(IN) to

eliminate the common mode signal.

Figure 3.8: Diagram block of the pseudo-differential amplifier. Image obtained from: [4]

With this topology a low voltage and wide swing is achieved, with a CM gain of -36db. The

explanation for the dimensioning of the circuit can be found here: [4]. The reader can find more

information about PDAs here: [16]

3.4 Low-Voltage Rail-to-Rail CMOS Differential Difference Amplifier [5] 31

3.4 Low-Voltage Rail-to-Rail CMOS Differential Difference Ampli-fier [5]

This article introduces a low-voltage rail-to-rail wide range CMOS Differential Difference Ampli-

fier (DDA). The input stage of this DDA comprises two rail-to-rail VI converters with large signal

handling capability. Constant transconductance is achieved through the use of two maximum-

current selecting circuits and an output subtraction stage. A maximum-current selecting circuit is

presented in figure 3.9:

Figure 3.9: Maximum current selecting circuit. Image obtained from: [5]

Where Iout will always take the maximum value of I1 or I2. The authors start by analysing the

DDA, analysis that was made in previous articles presented here. Then the rail-to-rail VI converter

is presented in figure 3.10:

32 Bybliographic Review

Figure 3.10: rail-to-rail V-I converter. Image obtained from: [5]

Through the transfer function of the circuit it is concluded that : I1− I2 = gmN(V1−V2), thus

achieving a V -I converter. Then, using these blocks previously referred, the authors build a rail-

to-rail DDA with a wider input voltage range, due to the use of the linear V-I converters. The

reader can find more information about low voltage amplifiers here: [17], [18] and [19].

3.5 A CMOS Chopper-Stabilized Differential Difference Amplifierfor Biomedical Integrated Circuits [6]

This articles presents a topology that is also convenient for biomedical applications, the chopper

topology. Its principle of operation is to modulate the input signal, to avoid the flicker noise (which

grows with the decrease of the signal’s frequency), and then demodulate it at the output. However,

in this article, the amplifier proposed is a mixed technique between chopper topology with DDA.

Image 3.11 contains the proposed CHSDDA (Chopper stabilized Differential Difference Am-

plifier):

3.6 System design of a low noise, low offset instrumentation amplifier with chopper stabilization[7] 33

Figure 3.11: Circuit Diagram of the CHSDDA. Image obtained from: [6]

In the end this topology presents very good characteristics, namely a high CMRR(Common-

mode rejection ratio) high gain and low noise. The reader can find more information about chopper

amplifiers here: [20] and [21].

3.6 System design of a low noise, low offset instrumentation amplifierwith chopper stabilization [7]

This document presents an instrumentation amplifier chopper stabilized with some good charac-

teristics. Some of them come from the fact that the amplifier used is fully differential. As referred

before, the chopper technique allows the diminishing of the flicker and thermal noise. In this par-

ticular case, a modulator and a demodulator are used, a BPF(band-pass filter) and a LPF(low-pass

filter), as well as a rail-to-rail input pre amplifier,which can be seen in the figure 3.12:

34 Bybliographic Review

Figure 3.12: Rail-to-rail input pre amplifier. Image obtained from: [7]

The modulator and the demodulator are implemented using CMOS switches, and as the name

may suggest, they modulate and demodulate the input signal as to increase or decrease the signal’s

frequency. The function of the band-pass filter is to reduce the residual offset which comes from

the charge injection of the input modulator, and the top priority is that the center frequency of the

band-pass filter should be very close to the oscillator frequency in order to achieve low residual

offset. And low-pass filter is just used to select the base-band signal and reject the harmonics. [7]

As for the instrumentation amplifier, the goal is to amplify the signal and try to diminish its input

noise level.

However, the results achieved by the author in terms of noise are a bit higher than expected, as

a 345nV/√

Hz is obtained at the frequency of 100Hz. It is proposed in the end as future work the

diminishing of the noise level, and higher gain stages for lower amplitude signals. The reader can

find more information about instrumentation amplifiers here: [22], [23], [24].

Chapter 4

Problem Presentation

As the reader may have noticed during the reading of this document, it is not easy to achieve a lot

of satisfactory characteristics in an amplifier topology. Most of the times it’s a trade-off between

power, bandwidth, CMRR, and a lot of other things, and the choice mostly comes depending of

the situation in which we are going to employ our amplifier. However, in this case there are some

restrictions, and we must have that in mind when choosing which path to take. For example, in

biomedical applications, a good CMRR must be above the 120db mark. Noise is critical, as we

want to maintain the signals in the most pure form.

With that in mind, the challenge of this work is to develop a versatile high gain instrumentation

amplifier, with a CMFB network that will be able to suppress most of these problems. Also, its

gain has to be sufficiently high, and his power supply as low as possible. It will be designed for

chip integration, so mostly the technology used will be the CMOS 0.35µm technology.

4.1 Preliminary topology for an instrumentation amplifier

It is presented in image 4.1 the preliminary topology for the instrumentation amplifier:

35

36 Problem Presentation

Figure 4.1: Initial amplifier proposal

As stated before, its input will come from the electrodes, and it consists of a small frequency

and small voltage signal. Ideally its output would be the same input signal with a larger voltage

but that is always not the case. This initial proposal consists of a differential amplifier, but the

goal is to achieve a fully differential amplifier, which can easily be achieved by including another

gain stage at the left of the amplifier and add another output. It has two stages, the input stage

and the gain/output stage. In the input we have two differential pairs, that are complementary

to each other. This is because when extreme input voltages are achieved, one input pair will be

disabled accordingly, thus making the PMOS pair deal with the most negative voltages, and the

NMOS deal with the most positive. Besides this, as previously explained the FDDA architecture

allows for great voltage swings. The resistors and the capacitors are employed for compensation

reasons. The active loads are employed with diode connected PMOS and NMOS, according to the

transistors to whom they load, as well as the bias network.

This topology lacks a CMFB network, and that is the next step to be taken in the evolution of

the project. As one can read in the sub chapter related to CMFB, its topology can be employed by

resistors and MOSFETs, but the goal is to develop perhaps a new topology with MOSFETS.

Chapter 5

Methodology and Work Plan

In the preparation for the Master thesis, a thorough study has been made on amplifiers and its

design. In the second semester the following tasks will be carried out to complete the Master

Thesis:

• Get familiar with the design and simulation tools, namely cadence

• Develop and simulate various CMFB networks, and see which fits best for the proposed

topology

• Study and development of the instrumentation amplifier

• Structural design and post-layout simulation of the amplifier

• Writing the final report for the master thesis

The work plan for the next semester can be found in figure 5.1 , which contains a gant chart:

37

38 Methodology and Work Plan

Figure 5.1: Gant chart of the work plan

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