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Aplicaccedilatildeo de Microprocessadores I

Aula 5

Temporizaccedilatildeo e Interrupccedilatildeo

Marcelo Andrade da Costa Vieira

AAAA

AA

Contagem de Tempo

AA

bull  Existem 3 maneiras de contarmos tempo com os microcontroladores PIC

ndash  Contando ciclo de maacutequina por meio de loopings ndash  Contando os ciclos de maacutequina por meio dos timers ndash  Contando pulsos externos por meio dos timers

Contando tempo

AA

bull  Loopings

ndash  Ciclo de maacutequina = 4 x 1fosc

ndash  Existem instruccedilotildees de 1 ciclo e de 2 ciclos

Contando tempo

AA

Temporizadores e Contadores

AA

Timers

bull  O microcontrolador PIC18F45K22A possui 7 Timers ndash  TMR0 Timer de 8 ou 16 bits com prescaler ndash  TMR135 Timers de 16 bits ndash  TMR246 Timers de 8 bits com prescaler e postscaler

AA

TMR0 bull  Timer de 8 ou 16 Bits bull  Utiliza o registrador (TMR0L e TMR0H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno

(ciclos de maacutequina = fosc4) bull  Tem prescaler ateacute 1256 bull  Utiliza os registradores

ndash  T0CON Configuraccedilotildees ndash  TMR0L ndash  TMR0H

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Contagem de Tempo

AA

bull  Existem 3 maneiras de contarmos tempo com os microcontroladores PIC

ndash  Contando ciclo de maacutequina por meio de loopings ndash  Contando os ciclos de maacutequina por meio dos timers ndash  Contando pulsos externos por meio dos timers

Contando tempo

AA

bull  Loopings

ndash  Ciclo de maacutequina = 4 x 1fosc

ndash  Existem instruccedilotildees de 1 ciclo e de 2 ciclos

Contando tempo

AA

Temporizadores e Contadores

AA

Timers

bull  O microcontrolador PIC18F45K22A possui 7 Timers ndash  TMR0 Timer de 8 ou 16 bits com prescaler ndash  TMR135 Timers de 16 bits ndash  TMR246 Timers de 8 bits com prescaler e postscaler

AA

TMR0 bull  Timer de 8 ou 16 Bits bull  Utiliza o registrador (TMR0L e TMR0H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno

(ciclos de maacutequina = fosc4) bull  Tem prescaler ateacute 1256 bull  Utiliza os registradores

ndash  T0CON Configuraccedilotildees ndash  TMR0L ndash  TMR0H

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

bull  Existem 3 maneiras de contarmos tempo com os microcontroladores PIC

ndash  Contando ciclo de maacutequina por meio de loopings ndash  Contando os ciclos de maacutequina por meio dos timers ndash  Contando pulsos externos por meio dos timers

Contando tempo

AA

bull  Loopings

ndash  Ciclo de maacutequina = 4 x 1fosc

ndash  Existem instruccedilotildees de 1 ciclo e de 2 ciclos

Contando tempo

AA

Temporizadores e Contadores

AA

Timers

bull  O microcontrolador PIC18F45K22A possui 7 Timers ndash  TMR0 Timer de 8 ou 16 bits com prescaler ndash  TMR135 Timers de 16 bits ndash  TMR246 Timers de 8 bits com prescaler e postscaler

AA

TMR0 bull  Timer de 8 ou 16 Bits bull  Utiliza o registrador (TMR0L e TMR0H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno

(ciclos de maacutequina = fosc4) bull  Tem prescaler ateacute 1256 bull  Utiliza os registradores

ndash  T0CON Configuraccedilotildees ndash  TMR0L ndash  TMR0H

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

bull  Loopings

ndash  Ciclo de maacutequina = 4 x 1fosc

ndash  Existem instruccedilotildees de 1 ciclo e de 2 ciclos

Contando tempo

AA

Temporizadores e Contadores

AA

Timers

bull  O microcontrolador PIC18F45K22A possui 7 Timers ndash  TMR0 Timer de 8 ou 16 bits com prescaler ndash  TMR135 Timers de 16 bits ndash  TMR246 Timers de 8 bits com prescaler e postscaler

AA

TMR0 bull  Timer de 8 ou 16 Bits bull  Utiliza o registrador (TMR0L e TMR0H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno

(ciclos de maacutequina = fosc4) bull  Tem prescaler ateacute 1256 bull  Utiliza os registradores

ndash  T0CON Configuraccedilotildees ndash  TMR0L ndash  TMR0H

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Temporizadores e Contadores

AA

Timers

bull  O microcontrolador PIC18F45K22A possui 7 Timers ndash  TMR0 Timer de 8 ou 16 bits com prescaler ndash  TMR135 Timers de 16 bits ndash  TMR246 Timers de 8 bits com prescaler e postscaler

AA

TMR0 bull  Timer de 8 ou 16 Bits bull  Utiliza o registrador (TMR0L e TMR0H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno

(ciclos de maacutequina = fosc4) bull  Tem prescaler ateacute 1256 bull  Utiliza os registradores

ndash  T0CON Configuraccedilotildees ndash  TMR0L ndash  TMR0H

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Timers

bull  O microcontrolador PIC18F45K22A possui 7 Timers ndash  TMR0 Timer de 8 ou 16 bits com prescaler ndash  TMR135 Timers de 16 bits ndash  TMR246 Timers de 8 bits com prescaler e postscaler

AA

TMR0 bull  Timer de 8 ou 16 Bits bull  Utiliza o registrador (TMR0L e TMR0H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno

(ciclos de maacutequina = fosc4) bull  Tem prescaler ateacute 1256 bull  Utiliza os registradores

ndash  T0CON Configuraccedilotildees ndash  TMR0L ndash  TMR0H

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

TMR0 bull  Timer de 8 ou 16 Bits bull  Utiliza o registrador (TMR0L e TMR0H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno

(ciclos de maacutequina = fosc4) bull  Tem prescaler ateacute 1256 bull  Utiliza os registradores

ndash  T0CON Configuraccedilotildees ndash  TMR0L ndash  TMR0H

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Registrador T0CON

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Diagrama TMR0

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Registradores para TMR0

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

TMR135

bull  Timer de 16 Bits bull  Utiliza 2 registradores (TMR1L e TMR1H) bull  Pode ser incrementado por pulso externo bull  Pode ser incrementado por CLK interno (ciclos de maacutequina) ou cristal externo exclusivo para os Timers 135 bull  Tem prescaler ateacute 18

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

TMR246

bull  Timer de 8 Bits bull  Incrementado apenas por CLK interno (ciclos de maacutequina) bull  Pode ser alterado o valor de estouro (limite de contagem) bull  Possui Prescaler (ateacute 116) e Postscaler (ateacute 116)

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Interrupccedilatildeo

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Interrupccedilatildeo

bull  Existem 34 fontes de interrupccedilatildeo no PIC18F45K22

bull  Externas (4) bull  Overflow de timer (7) bull  Comunicaccedilatildeo (serial paralela) bull  Conversor AD bull  PWM bull  Comparador (CCP) bull  Escrita na EEPROM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Interrupccedilatildeo

bull  Parada (via hardware) do programa em fase de execuccedilatildeo

bull  Volta ao ponto que estava antes da interrupccedilatildeo (pilha)

bull  Atende agrave acontecimentos assiacutencronos (sem instruccedilatildeo de chamada no programa) bull  Subrotina eacute siacutencrona

bull  Diferentes prioridades

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Interrupccedilatildeo - PIC

bull  Para cada interrupccedilatildeo 3 bits que devem ser configurados

ndash  IE (Interrupt Enable) ndash Habilitaccedilatildeo (chaves individuais) ndash  IF (Interrupt Flag) - Sinalizaccedilatildeo ndash  IP (Interrupt Priority) - Prioridade

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Interrupccedilatildeo - PIC

bull  Registradores ndash  INTCON INTCON1 INTCON2 - Chaves gerais de

habilitaccedilatildeo e os bits de controle de interrupccedilotildees baacutesicas (externas e TMR0)

ndash  PIE1 PIE5 ndash Peripheral Interrupt Enable (IE) ndash  PIR1 PIR5 ndash Peripheral Interrupt Request (IF) ndash  IPR1 IPR5 ndash Interrupt Priority Register (IP) ndash  RCON ndash Habilitar niacuteveis de prioridades (simnatildeo) ndash IPEN

bull  IPEN = 1 (Habilita niacuteveis de interrupccedilatildeo) bull  IPEN = 0 (Desabilita niacuteveis de interrupccedilatildeo)

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Interrupccedilatildeo - PIC

bull  Chaves ndash  Habilitaccedilatildeo (enable)

bull  Chave geral ou Chave geral de alta prioridade (GIEGIEH) bull  Chave perifeacutericos ou Chave geral de baixa prioridade (PEIEGIEL) bull  Chaves individuais (TMR0IE RBIE ADIE TXIE )

bull  Flags de aviso (TMR0IF RBIF ADIF TXIF ) bull  Prioridade (TMR0IP RBIP ADIP TXIP )

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Registrador INTCON

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

bull  Se o evento ocorre o flag eacute setado (SEMPRE) bull  Verifica se a chave individual daquela interrupccedilatildeo estaacute

setada (e as chaves gerais tambeacutem) bull  Se estiverem o programa eacute desviado para o endereccedilo

0x0008h (Alta Prioridade) ou 0x0018h (Baixa Prioridade) bull  Vc deve apagar o flag correspondente antes de retornar

ao programa principal

Os flags satildeo setados independente da interrupccedilatildeo estar habilitada mas nunca satildeo apagados via hardware

Tratamento da Interrupccedilatildeo

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Interrupccedilatildeo - Passos

Isso eacute feito automaticamente

Isso eacute feito automaticamente

Deve-se zerar o flag

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Portas I0

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Portas de I0

bull  Definir se eacute entrada ou saiacuteda (TRISA TRISB etc) bull  Quando for escrever na porta (saiacuteda) usar os registradores LATA

LATB etc bull  Quando for ler o estado de um pino (entrada) usar os registradores

PORTA PORTB etc bull  Definir se a porta eacute analoacutegica ou digital devido ao conversor AD

(ANSELA ANSELB etc)

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

Portas de I0

AA

Portas de I0

curren 2010-2012 Microchip Technology Inc DS41412F-page 135

PIC18(L)F2X4XK22100 IO PORTSDepending on the device selected and featuresenabled there are up to five ports available All pins ofthe IO ports are multiplexed with one or more alternatefunctions from the peripheral features on the device Ingeneral when a peripheral is enabled that pin may notbe used as a general purpose IO pin

Each port has five registers for its operation Theseregisters are

bull TRIS register (data direction register)bull PORT register (reads the levels on the pins of the

device)bull LAT register (output latch)bull ANSEL register (analog input control)bull SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-write operations on the value that the IO pins aredriving

A simplified model of a generic IO port without theinterfaces to other peripherals is shown in Figure 10-1

FIGURE 10-1 GENERIC IO PORT OPERATION

101 PORTA RegistersPORTA is an 8-bit wide bidirectional port Thecorresponding data direction register is TRISA Settinga TRISA bit (= 1) will make the corresponding PORTApin an input (ie disable the output driver) Clearing aTRISA bit (= 0) will make the corresponding PORTApin an output (ie enable the output driver and put thecontents of the output latch on the selected pin)

Reading the PORTA register reads the status of thepins whereas writing to it will write to the PORT latch

The Data Latch (LATA) register is also memory mappedRead-modify-write operations on the LATA register readand write the latched output value for PORTA

The RA4 pin is multiplexed with the Timer0 moduleclock input and one of the comparator outputs tobecome the RA4T0CKIC1OUT pin Pins RA6 andRA7 are multiplexed with the main oscillator pins theyare enabled as oscillator or IO pins by the selection ofthe main oscillator in the Configuration register (seeSection 241 ldquoConfiguration Bitsrdquo for details) Whenthey are not used as port pins RA6 and RA7 and theirassociated TRIS and LAT bits are read as lsquo0rsquo

The other PORTA pins are multiplexed with analoginputs the analog VREF+ and VREF- inputs and thecomparator voltage reference output The operation ofpins RAlt30gt and RA5 as analog is selected by settingthe ANSELAlt5 30gt bits in the ANSELA register whichis the default setting after a Power-on Reset

Pins RA0 through RA5 may also be used as comparatorinputs or outputs by setting the appropriate bits in theCM1CON0 and CM2CON0 registers

The RA4T0CKIC1OUT pin is a Schmitt Trigger inputAll other PORTA pins have TTL input levels and fullCMOS output drivers

The TRISA register controls the drivers of the PORTApins even when they are being used as analog inputsThe user should ensure the bits in the TRISA registerare maintained set when using them as analog inputs

EXAMPLE 10-1 INITIALIZING PORTA

DataBus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

InputBuffer

IO pin(1)QD

CK

QD

CK

EN

Q D

EN

RD LAT

or Port

Note 1 IO pins have diode protection to VDD and VSS

TRISx

ANSELx

Note On a Power-on Reset RA5 and RAlt30gtare configured as analog inputs and readas lsquo0rsquo RA4 is configured as a digital input

MOVLB 0xF Set BSR for banked SFRsCLRF PORTA Initialize PORTA by

clearing output data latches

CLRF LATA Alternate method to clear output data latches

MOVLW E0h Configure IO MOVWF ANSELA for digital inputsMOVLW 0CFh Value used to

initialize data direction

MOVWF TRISA Set RAlt30gt as inputs RAlt54gt as outputs

AA

FIM

AA

FIM