Capacitor Charge Control Technique Applied to Digitally Programmable IIR Switched-Capacitor Filter

Joarez B. Monteiro Antonio Petraglia Carlos A. Leme EE/COPPE - Universidade Federal do Rio de Janeiro

C.P 68504, CEP 21945-970 Rio de Janeiro, RJ

Brazil

EE/COPPE - Universidade Federal do Rio de Janeiro

C.P 68504, CEP 21945-970 Rio de Janeiro, RJ,

Brazil

Grupo de Circ. e Sist. Integrados

Instituto Superior Técnico Av. Rovisco Pais 1, 1096 Lisboa,

Portugal joarez@lps.ufrj.br petra@pads.ufrj.br carlos@gcsi.ist.utl.pt

Abstract

This paper presents a novel procedure for the implementation of digitally programmable switched-capacitor recursive (IIR) filters. The use of a reduced number of poles assures low sensitivity in the passband, being better than that obtained with an elliptic filter. The response of the proposed structure − a couple of poles and four couples of zeros − is similar a fifth order elliptic filter. Digital-to-analog conversion (DAC) techniques allow filter programming by controlling capacitor charge instead of adjusting a capacitor bank, reducing both silicon area and costs. Multiplexing individual operational amplifiers among 2nd order FIR modules reduces the number of required op-amps and, consequently, power dissipation. The effects of charge injection and operational amplifier offset voltages are greatly reduced by using a totally differential filter structure. Emphasis in solutions to parasitic grounded capacitance problems is presented.

1. Introduction

The high-density integration, low-power consumption and high-speed characteristics of CMOS technology, associated to the low complexity of switched-capacitor (SC) circuits, have been a strong stimulus to compacting systems using a mixed analog-digital integration technique [1]. Switched-capacitors circuits have been broadly used in filtering applications where programmability is an attractive and desired characteristic to several researchers [2]-[6].

The main objective of this paper is to present a novel switched-capacitor structure that realizes a digitally programmable filter, which is appropriate to integrated circuit implementations. The structure choice was based

on characteristics, such as low sensitivity to capacitor ratio errors, simpler coefficient programmability and low-power consumption, that turn it appropriate to integrated circuits.

Switched-capacitor filters should have a low sensitivity to the coefficient changes – capacitor ratios – that depends, besides other factors, on the filter structure used in the implementation. A comparative study reported in [2][7] has shown that the use of recursive (IIR) SC structures having transfer functions with the number of poles smaller than the number of zeros yields low sensitivity with respect to capacitance ratios. Sensitivity of these structures is better than those achieved by ladder realizations of elliptic transfer functions. Additional advantages include approximately linear phase in the passband, smaller power consumption and noise [2].

In general, capacitor banks are used in SC programmable filters. Switches controlled by digital codes allow associating capacitors that control the coefficients of the filter. This procedure, however, is not convenient for integrated circuit realizations, since the resulting structures usually occupy large silicon area, increasing production costs. Capacitor banks also present some characteristics that contribute to filter coefficients errors: the parasitic capacitance associated to the great number of capacitors, the parasitic capacitance change while programming the filter and the large spread of capacitor values [3].

Filter programming in the proposed structure is made by using a digital-to-analog conversion (DAC) technique [6] to control capacitance charge, instead of capacitance area, as in the conventional approach [3]. As a consequence, in addition to its simpler coefficient programmability characteristics, the proposed solution leads to lower capacitance spread and substantially smaller silicon area. It is important to observe that low dispersion improves the capacitor ratio precision and

Proceedings of the 15 th Symposium on Integrated Circuits and Systems Design (SBCCI’02) 0-7695-1807-9/02 $17.00 © 2002 IEEE

demands smaller operational amplifier (op amp) output current, reducing power consumption.

Although it increases the silicon area, the totally differential topology implementation was motivated by its advantageous characteristics of offset voltage cancellation, reduction of the charge injection effects, besides increase in dynamic range. In addition, it allowed bypassing some parasitic capacitance problems observed in [8], as shown in Sections 2 and 3.

Topologically identical second-order finite impulse response (FIR) sections are used as basic building blocks, with a single multiplexed op amp, to realize zeros and poles of the filter, leading to a quite attractive structure to integrated circuit implementation for its modularity and low consumption.

In order to verify the practical viability of the proposed technique, a filter has been designed with eight zeros on the unit circle and only two complex poles [9]. Observe that the number of poles plus the number of zeros is equal to what is obtained in the equivalent elliptic approximation.

2. Filter Structure

Four second-order FIR SC cells are cascaded in the forward path to implement the transfer function zeros. Each one has transfer function of the form 1+αzz

-1 +z-2 guaranteeing that zeros are kept on the unit circle bounds (|z|=1), by controlling a single coefficient (αz) in the interval [-2, 2].

Fischer has presented structures for the realization of FIR SC filters by a single multiplexed op amp in [10][11], where (n+1) clock phases are used to implement order n polynomials. This way, adders and delay lines are implemented without excessive power consumption.

+

-

1

1C1

C2

C3

C0

C4

C5

1

1

1

1

1

11

2 2

23

3 3

3

3

3Ve Vs

���

����� +−

+−= −− 21

3

54

1

01 zz

C

CC1

C

C(z)H

Fig.1. Second-order FIR SC cell for zeros

realization.

Based on this study, we have designed the FIR cell shown in Fig. 1, to implement the above second-order polynomial using 3 clock-phases, and to allow the programmability of the coefficient αz.

Positive and negative coefficients are realized by connecting capacitors C4 and C5 in parallel during the sampling mode, and reversing C4 during the transfer mode, so that the coefficient αz is implemented as a difference between two capacitance ratios, as given by H1(z) in Fig. 1. By varying C4, with C5 fixed as a reference, positive and negative coefficients can be obtained without modifying the cell structure. Changes in capacitor C4 are implemented by using a digital-analog conversion technique (DAC) described in the Section 3.

2

Vs

+

-

5

5C1

C2

C3

C4

C5

1

1

1

1 1

22

23

33

3

3

C0 2

3

3

2

+

-C1

2

2

1

C1

2

1

CVe

X(z) Y(z) +

H2(z)

����� +⋅−−= −− 2

1

01

1

0

3

542 z

C

Cz

C

C

C

CC(z)H

21p2 z

�z

� 1

1

(z)H1

1

X(z)

Y(z)−− ++

=−

=

The condition for the realization of complex poles is:

�2

���2 p ≤≤−

The condition for the stability is:

1

�01

�z <≤�<=

Fig. 2. Second-order FIR SC cell for pole

realizations.

Proceedings of the 15 th Symposium on Integrated Circuits and Systems Design (SBCCI’02) 0-7695-1807-9/02 $17.00 © 2002 IEEE

Another important characteristic of the circuit of Fig. 1, which is particularly desirable for programmable filters, is the structural realization of the unitary coefficients of the z0 and z-2 terms. Independently of any capacitor mismatch, it is guaranteed that the zeros will be exactly on the unit circle, yielding maximum attenuation in the stopband.

The poles are realized by introducing a minor change in the above cell structure, as indicated in Fig. 2, with the purpose of eliminating the independent term of H1(z) to form the polynomial H2(z). The resulting network is then placed in a feedback loop to implement the desired poles.

The transfer function denominator is programmed by adjusting capacitances C0 and C4, to control, respectively, the coefficients β and αp.

Fig. 3 shows the global proposed filter structure, which realizes a pair of complex poles and four pairs of complex zeros. Due to its high gain, the feedback cell should be cascaded as a last stage as shown Fig. 3, that is, after all cells for zeros, to compensate previously accumulated losses, and avoid distortion at the op amp output, due to signal saturation. For simplicity, the filter structure is presented at single ended version. However, it is being designed in totally differential structure so that, besides increasing the dynamic range, it reduces the effects of charge injection and cancels the undesirable effects of the op amp offset voltage. In order to avoid the sensitivity to grounded parasitic capacitance, the connections of C2 capacitor were changed, making use of the fully differential structure advantages, as shown in Fig. 4.

C21

2 2

virtualground

(-)

virtualground

(+)

op ampoutput

(+)1

Fig. 4. Insensitive capacitor C2 structure. 3. DAC programming

The filter programming is allowed by the adjustment of the capacitors C4 in the four cells for zeros and of capacitors C0 and C4 in the cell for poles. They control, respectively, the αz, β and αp coefficients. The conventional approach for the design of programmable SC filters consists of digitally controlling capacitor banks, in a procedure that is equivalent to physically modifying capacitor sizes. In addition to requiring a large capacitance spread, these solutions lead to excessive consumption of silicon area and power. With the purpose of reducing the number of capacitors and the capacitance spread, the approach presented here uses a DAC technique to emulate the variation of a capacitance value by controlling its charge instead of its physical size.

In Fig. 5, an illustrative circuit and its respective time diagram are shown. It is verified below that the final voltage stored at capacitor Cb depends on two factors: the input voltage (Ve) and the N-bit binary control word applied to the system.

Fig. 3. Global structure: 2 poles and 8 zeros filter

2

Vs

+

-

5

5C1

C2

C3

C4

C5

1

1

1

1 1

22

23

33

3

3

C0 2

3

3

2

+

-C1

2

2

1

C1

2

1

C

+

-

1

1C

1

C2

C3

C4

C5

1

1

1

11

2 2

23

3 3

3

3

C01

3+

-

2

2C

1

C2

C3

C4

C5

1

1

1

11

2 2

23

3 3

3

3

C01

3

+

-

3

3C1

C2

C3

C4

C5

1

1

1

11

2 2

23

3 3

3

3

C01

3+

-

4

4C1

C2

C3

C4

C5

1

1

1

11

2 2

23

3 3

3

3

C01

3

Ve

Proceedings of the 15 th Symposium on Integrated Circuits and Systems Design (SBCCI’02) 0-7695-1807-9/02 $17.00 © 2002 IEEE

+

-

S.bi

S.bi

TEOC

SO

C

Ca Cb

Cc

VeVs

b0 bN-1b1

conversion period EOCSOC

S

T

bi

Fig. 5. Basic DAC structure and time diagram. The duration of the conversion process is determined

by the time elapsed between the end of the pulse (SOC - start of conversion) and the beginning of the pulse (EOC - end of conversion).

The charge and discharge operations of capacitor Cb are controlled during the conversion period by the sequences of pulses S and T, and by the N-bit digital word. For each pulse in S, the switches S�bi and S� ib are closed when bi = 1 and bi = 0, respectively, where bi is the i-th bit of the programming digital word. If bi = 1, then Ca is charged with the input voltage, Ve; if bi = 0, then Ca is discharged. During pulse T, the capacitors Ca and Cb are connected in parallel and their charges are redistributed, then modifying the voltage stored in Cb. This process is repeated during the whole conversion period, for each bit of the programming word.

For each pulse in S, the electric charges accumulated in the capacitors Ca and Cb will be:

�� �−=

==

−==

1)1,2,3...(Ni,CV

0i,0Q

1)1,2,3...(N,0i,bCVQ

1-i

Cbi

ieCai

(1)

After each pulse in T, the electric charge stored in the

equivalent capacitor (Ceq=Ca+Cb) it will be same to the sum of the electric charges of Ca and Cb before closing the switch T, that is:

Cbi

Caiieq

Ceqi QQVCQ +== (2)

Assuming Ca=Cb=C � Ceq=2C, we can write:

2-N1-Ne1-Neq

01e1eq

0e0eq

CVbCVVC

CVbCVVC

bCVVC

+=

+=

=

�

The final voltage VN-1 stored in Ceq can be determined

by Eq. 3 :

eN

1N

0ii

i

e1-N KV2

b2

VV ==

� −

= (3)

At the end of the conversion period, the pulse EOC

makes the transfer of load of the capacitor Cb for Cc. Like this, the exit tension Vs will be given by Eq. 4:

Finally, the pulse EOC transfers to Cc the charge stored in Cb, yielding the output voltage Vs (Eq. 4), reminding that VN-1 is, also, the tension stored in Cb:

ec

b1-N

c

bs V

C

KCV

C

CV −=−= (4)

This expression shows that the above technique has the

effect of scaling the capacitance Cb by the factor K, which is determined by the programmed N bits binary word.

In the time diagram of the Fig. 5, It can be observed that the duration of the conversion period corresponds to N periods of the signal S plus a half one as a stabilization time for the op amp output. N is the number of bits used in the operation of DAC. Then, for this 3-phases circuit, the sampling frequency should be at least 3(N+0.5) times smaller than the frequency of the signal S, that is, at least 25,5 times smaller for N=8 bits. This limitation in the maximum operation frequency of the filter is, maybe, the main disadvantage in using this technique.

Still in Fig. 5, it can be observed that the nodes A and B are sensitive to grounded parasitic capacitances, leading to charge transfer errors among the capacitors Ca, Cb and Cc. Fig. 6 presents the final structure that substitutes C4 to allow filter programmability. In order to meet Hasler conditions [12], connections with Cb were modified to make it insensitive to grounded parasitic capacitances. Although the node A continues sensitive, careful layout design guarantees the balance between grounded capacitances associated to the nodes A and B [13] and, consequently, the correct operation of the DAC. Because of these modifications, the voltage stored in Cb is inverted. Since a differential structure is used, the convenient virtual ground choice to realize the desired polarity inversion at the transfer phase is allowed.

Proceedings of the 15 th Symposium on Integrated Circuits and Systems Design (SBCCI’02) 0-7695-1807-9/02 $17.00 © 2002 IEEE

In the cells for zeros, the SOC pulse, the conversion period and the EOC pulse are the phases 2, 3 and 1, respectively.

S.bi

S.bi

T(EOC)

1

(SO

C)

24C

4C3

op ampoutput

(+)

virtualground

(-)

(EO

C)

1 3

A

(SO

C)

2

B

Fig. 6. Structure of C4.

The final structure for the capacitor C0 in cell for poles

is shown in Fig. 7. The conversion period occurs in phase 2, and SOC and EOC pulses in phases 1 and 3, respectively.

S.bi

S.bi

T(EOC)

2

(SO

C)

1

C

C2

adderoutput

(+)

virtualground

(+)

(EO

C)

2 3

(SO

C)

1

Fig. 7. Structure of Co (cell for poles)

4. Simulation results

To verify the key theoretical and practical aspects of the proposed approach, the lowpass filter with 8 zeros and 2 poles has been designed, using the optimization software iirremez.m [9], satisfying the following specifications: passband ripple of 1.0 dB, stopband attenuation above 50 dB and normalized passband edge frequency equal to 0.3. The corresponding diagram of poles and zeros is given in Fig. 8.

-1 -0.5 0 0.5 1

-1

-0.5

0

0.5

1

Real part

Ima

gin

ary

pa

rt

Fig. 8. Poles and zeros diagram of the proposed filter.

Five second-order cells compose the structure: 4 cascaded cells (see Fig. 1) in the forward path to realize the zeros, and 1 cell as in Fig. 2, to realize the pair of poles. A modular aspect of this structure is particularly suitable for integrated circuit implementations. By using 8-bit wordlengths to program the filter coefficients, it is possible to control them in steps of 1/256. It can be observed in Fig. 9 that the zeros of the programmed filter remain on the unit circle, as predicted, and that its frequency response deviation with respect to the ideal one is very small.

The proposed filter has been designed considering a sampling rate fs=1 MHz, and simulated using parameters of a 0.8µm CMOS AMS fabrication process. The simulations have shown that the op amps gains should be larger than 5000 (74dB), to avoid finite DC gain effects. The results obtained with folded cascode OTAs in differential configuration, specially designed for this application, having DC gain of 107dB, gain-bandwidth product of 110MHz and phase margin of 77 degrees, have confirmed the viability of the proposed technique in integrated circuit implementations. The frequency response obtained using PSPICE database is shown in Fig. 10, in terms of the normalized frequency f/2fs, and is in very close agreement with the theoretical one.

0 0.05 0.1 0.15 0.2 0.25 0.3

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

ma

gn

itud

e (

dB

)

normalized frequency

ideal programmed

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-90

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

ma

gn

itud

e (

dB

)

normalized frequency

ideal programmed

Fig. 9. Frequency responses of the ideal filter and programmed filter with an 8-bit word.

Proceedings of the 15 th Symposium on Integrated Circuits and Systems Design (SBCCI’02) 0-7695-1807-9/02 $17.00 © 2002 IEEE

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Normalized Frequence (f/2fs)

Mag

nitu

de (

dB)

SimulatedIdeal

Fig. 10. Frequency response obtained by PSPICE simulation.

5. Conclusions

The results obtained show that the proposed structure can be used with advantages in the realization of digitally programmable filters, when compared to other reported approaches. Transfer functions with a small number of poles yield low sensitivity to coefficient errors. The control of capacitances by the DAC technique described allows direct coefficient programmability, leads to solutions with small capacitance spread, and, as a result, to savings in silicon area and power consumption. These characteristics, allied to the modularity of the resulting structure, make the proposed approach suitable for the realization of monolithic programmable filters.

The multiplexing technique employed to reduce the number of op amps enables the use of the programmable filter in low power applications. On the other hand, using 8 bits of resolution, for instance, the sampling rate required for the DAC is 25.5 times the filter sampling rate, limiting the maximum operation frequency of the filter.

6. References [1] R. Gregorian and G. Temes, �Analog MOS Integrated

Circuits for Signal Processing� New York: Wiley, 1986. [2] A. Petraglia and J. S. Pereira, �Switched-capacitor

decimation filters with direct-form polyphase structure having very small sensitivity characteristics�, Proc. Int. Symp. on Circuits and Systems, Orlando, Fl, EUA, pp. II.73-II.76, May 1999.

[3] U. Moon, �CMOS High-Frequency Switched-Capacitor Filters for Telecommunication Applications�. IEEE Journal of Solid-State Circuits, Vol. 35, No. 2, pp. 212-220, 2000.

[4] F. P. Martins, N. F. Paulino and, J. E. Franca, �Charge Programming Techniques for SC Biquads�. Proc. IEEE ISCAS93, Chicago, IL, pp. 1160-1163, 1993.

[5] A. Petraglia and S. K. Mitra, �Switched-Capacitor Equalizer with Digitally Programmable Tuning Characteristics�. IEEE Transactions on Circuits and Systems, vol. 38, No. 11, pp. 1322-1331, 1991.

[6] N. Paulino, J. E. Franca and F. P. Martins, �Programmable CMOS switched-capacitor biquad using quasi-passive algorithmic DAC’s�, IEEE Journal of Solid-State Circuits, Vol. 30, No. 6, 1995.

[7] A. Petraglia, �Fundamental frequency response bounds of direct form switched-capacitor filters with capacitance mismatch�, IEEE Trans. on Circuits and Systems, Part II, Vol. 48, pp. 340-350, Apr. 2001.

[8] J. B. Monteiro, A. Petraglia, C. A. Leme, �A Digitally Programmable IIR Switched-Capacitor Filter for CMOS Technology�, Proc. Int. Symp. on Circuits and Systems, Sydney, Au, pp. I.69-I.72, May 2001.

[9] L. B. Jackson, �An improved Martinez/Parks algorithm for IIR design with unequal numbers of poles and zeros�, IEEE Transactions on Signal Processing, Vol. 42, No. 5, 1994.

[10] G. Fischer, �Analog FIR filters by switched-capacitor techniques�, IEEE Transactions on Circuits and Systems, vol. 37, No. 6,1990.

[11] G. Fischer, �Switched-capacitor FIR filters – A feasibility study�, IEEE Transactions on Circuits and System � II: Analog and Digital Signal Processing, Vol.41, No. 12, 1994.

[12] M. Hasler, �Stray insensitive switched capacitor filters�, Proc. IEEE International Symposium on Circuits and Systems, Vol. 17, pp. 195-197, 1981.

[13] Dias, V. F., and Franca, J. E., �Parasitic-compensated switched-capacitor delay lines�. Electonic Letters, Vol. 24, pp. 377-379, 1988.

Normalized Frequency (f/2fs)

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