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MC602 – 2011 1
IC-UNICAMP MC 602
IC/Unicamp
2011s2Prof Mario Côrtes
VHDL
Máquina de Estados (FSM)
MC602 – 2011 2
IC-UNICAMPTópicos
• Máquinas de estados– Moore– Mealy
• Dois templates para implementação em VHDL
MC602 – 2011 3
IC-UNICAMP
Combinational circuit
Flip-flops
Clock
Q
W Z
Combinational circuit
Forma geral de um circuito síncrono
MC602 – 2011 4
IC-UNICAMPMáquina de Moore
C z 1 = ⁄⁄⁄⁄
Reset
B z 0 = ⁄⁄⁄⁄A z 0 = ⁄⁄⁄⁄w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0
MC602 – 2011 5
IC-UNICAMP
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
C z 1 = ⁄⁄⁄⁄
Reset
B z 0 = ⁄⁄⁄⁄A z 0 = ⁄⁄⁄⁄w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
Diagrama de Estados
MC602 – 2011 6
IC-UNICAMP Implementação
Combinationalcircuit
Combinationalcircuit
Clock
y2
z
wy1Y1
Y2
MC602 – 2011 7
IC-UNICAMPAtribuição de Estado
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 Y 2 Y 1
z
A 00 00 01 0
B 01 00 10 0
C 10 00 10 1
11 dd dd d
MC602 – 2011 8
IC-UNICAMP
w 00 01 11 10
0
1
0
1 0
y
2
y
1
Y 1
wy 1 y 2 =
w 00 01 11 10
0
1
0 d
1 d
y 2
y 1
Y 2
wy1
y 2 wy 1 y 2
+ =
d
d
0
0
0
0
0
0
1
0 1
0
1
0
d
y 1
z y 1 y 2
= 0
1
y 2
Y 1
wy 1 y 2 =
Y 2
wy1
wy2
+ =
z y 2
=
w y 1
y 2
+ ( ) =
Ignoring don't cares Using don't cares
Derivação das expressões lógicas
MC602 – 2011 9
IC-UNICAMP
D Q
Q
D Q
Q
Y 2
Y 1 w
Clock
z
y 1
y 2
Resetn
Circuito sequencial
MC602 – 2011 10
IC-UNICAMP
t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10
1
0
1
0
1
0
1
0
Clock
w
y 1
y 2
1
0 z
Timing diagram
MC602 – 2011 11
IC-UNICAMPFSM de Moore
USE ieee.std_logic_1164.all;
ENTITY simple ISPORT (Clock, Resetn, w : IN STD_LOGIC;
z : OUT STD_LOGIC );END simple;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C); -- Tipo Enumerado para
-- definir os EstadosSIGNAL y : State_type;
BEGINPROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THEN -- A é o estado inicial y <= A;
ELSIF (Clock'EVENT AND Clock = '1') THEN
con’t ...
MC602 – 2011 12
IC-UNICAMP
FSM de MooreCASE y IS
WHEN A =>IF w = '0’
THEN y <= A;ELSE y <= B;
END IF;WHEN B =>
IF w = '0’THEN y <= A;ELSE y <= C;
END IF;WHEN C =>
IF w = '0' THEN y <= A;ELSE y <= C;
END IF;END CASE;
END IF;END PROCESS;
z <= '1' WHEN y = C ELSE '0';END Behavior;
MC602 – 2011 13
IC-UNICAMP FSM de Moore - Simulação
MC602 – 2011 14
IC-UNICAMPFSM de Moore - Simulação
MC602 – 2011 15
IC-UNICAMP
FSM de MooreCodificação Alternativa (2 processos)
USE ieee.std_logic_1164.all;
ENTITY simple IS
PORT (Clock, Resetn, w : IN STD_LOGIC;
z : OUT STD_LOGIC );
END simple;
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C);
SIGNAL y_present, y_next : State_type;
MC602 – 2011 16
IC-UNICAMP
FSM de MooreCodificação Alternativa (2 processos)
BEGINPROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THENy_next <= A;
ELSEy_next <= B;
END IF;WHEN B =>
IF w = '0' THENy_next <= A;
ELSEy_next <= C;
END IF;
MC602 – 2011 17
IC-UNICAMPFSM de Moore - Codificação Alternativa
WHEN C =>IF w = '0' THEN
y_next <= A;ELSE
y_next <= C;END IF;
END CASE;END PROCESS;
PROCESS (Clock, Resetn)BEGIN
IF Resetn = '0' THENy_present <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THENy_present <= y_next ;
END IF;END PROCESS;
z <= '1' WHEN y_present = C ELSE '0';END Behavior;
MC602 – 2011 18
IC-UNICAMP
FSM - Especificando a Atribuição de Estados
ARCHITECTURE Behavior OF simple IS
TYPE State_TYPE IS (A, B, C);
ATTRIBUTE ENUM_ENCODING : STRING;
ATTRIBUTE ENUM_ENCODING OF State_type: TYPE IS "00 01 11";
SIGNAL y_present, y_next : State_type;
BEGIN
con’t ...
• Obs: Atributo Enum_Encoding é específico da ferramenta Quartus. Esta solução pode não funcionar em outras ferramentas CAD
MC602 – 2011 19
IC-UNICAMP
LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY simple IS
PORT ( Clock, Resetn, w : IN STD_LOGIC;z : OUT STD_LOGIC );
END simple;ARCHITECTURE Behavior OF simple IS
SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNT O 0);CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
BEGINPROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THEN y_next <= A;ELSE y_next <= B;END IF;
… con’t
FSM - Especificando a Atribuição de Estados
MC602 – 2011 20
IC-UNICAMP
WHEN B =>IF w = '0' THEN y_next <= A;ELSE y_next <= C;END IF;
WHEN C =>IF w = '0' THEN y_next <= A;ELSE y_next <= C;END IF;
WHEN OTHERS =>y_next <= A ;
END CASE;END PROCESS;
PROCESS ( Clock, Resetn )BEGIN
IF Resetn = '0' THENy_present <= A;
ELSIF (Clock'EVENT AND Clock = '1') THENy_present <= y_next;
END IF;END PROCESS;z <= '1' WHEN y_present = C ELSE '0';
END Behavior;
FSM - Especificando a Atribuição de Estados
MC602 – 2011 21
IC-UNICAMP
A
w 0 = z 0 = ⁄⁄⁄⁄
w 1 = z 1 = ⁄⁄⁄⁄B w 0 = z 0 = ⁄⁄⁄⁄
Reset
w 1 = z 0 = ⁄⁄⁄⁄
Máquina de Mealy
MC602 – 2011 22
IC-UNICAMPFSM de Mealy
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY mealy ISPORT (Clock, Resetn, w : IN STD_LOGIC;
z : OUT STD_LOGIC );
END mealy;
… con’t
MC602 – 2011 23
IC-UNICAMPFSM de Mealy
ARCHITECTURE Behavior OF mealy ISTYPE State_type IS (A, B);SIGNAL y : State_type;
BEGINPROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THEN y <= A;ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y ISWHEN A =>
IF w = '0' THEN y <= A;ELSE y <= B;END IF;
WHEN B =>IF w = '0' THEN y <= A;ELSE y <= B;END IF;
END CASE;END IF;
END PROCESS;… con’t
MC602 – 2011 24
IC-UNICAMPFSM de Mealy
PROCESS ( y, w )BEGIN
CASE y ISWHEN A =>
z <= '0';WHEN B =>
z <= w;END CASE;
END PROCESS;END Behavior;
