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© Reinaldo Bergamaschi
Sintese de Hardware em Alto Nivel
Reinaldo Bergamaschi
Disciplina MO801BHorario: 2a-feira (sala 301) e 4a-feira (sala 322)
das 14hs as 16hs
http://www.ic.unicamp.br/~rberga/MO801B_pagina_do_curso.html
© Reinaldo Bergamaschi
Carga Horária e Avaliação
� Carga Horaria: 30 aulas x 2h, incluindo aulas, apresentações de alunos e avaliações
� 3 Trabalhos em grupo (60% da nota final)Leitura de artigos
Codificacao de algoritmos
Escrita de artigo
Apresentacao em classe
� 4 Trabalhos Individuais (40% da nota final)Ler 4 artigos, escrever revisao e apresentar 2 deles em classe
15% p/ cada revisao, 20% p/ cada apresentacao
© Reinaldo Bergamaschi
Contato e Atendimento
� Email: rberga@ic.unicamp.brLinha de assunto deve comecar com o numero do curso seguido do assunto. Exemplo: MO801B: enviando trabalho T1
� Atendimento em pessoa: 2a’s e 4a’s de manhã, ou nos dias marcados p/ atendimento, ou via email a qualquer hora.
© Reinaldo Bergamaschi
O Que Voce Vai Aprender Nesse Curso….
Sintese de HW em Alto Nivel
operations, variables, signals, arrays, etc.
scheduling, allocation, pipelining, partitioning, etc.
registers, functional units, multiplexers, buses, memories, etc.
HDL
wait until not clk'stable and clk=1;if (cond1) then a <= b + c;else
a <= b - c; end if;for i in 0 to n loop...
X<
-
Y
Clk
RTL
Definicao:A transformacao de uma especificacao comportamental, algoritmica, e/ou funcional em uma rede de portas logicas que realizem e implementem a funcionalidade exata de tal especificacao.
© Reinaldo Bergamaschi
Ementa
� Introducao a sintese de circuitos digitais e ASICs
� Y-Chart e Niveis de abstracao: Comportamental, Estrutural e Fisico.
� Modelamento e representacoes: grafos, FSMs, rede logica, etc.
� Introducao a hardware description languages (HDLs), VHDL
� Introducao a grafos de controle e de fluxo de dados (CDFGs - Control and data-flow graphs) e representacoes equivalentes
� Compilacao de HDLs em CDFGs
� Analise de fluxo de dados em grafos CDFGs
� De CDFGs a hardware
� Algoritimos de escalonamento e geracao da maquina de estados-finitos
� Algoritimos de alocacao e geracao do data-path
� Algoritimos para compartilhamento de hardware e otimizacao de unidades funcionais
� Algoritimos especializados (potencia, timing)
� Metodologia e aspectos praticos
� Topicos em Sintese Logica
© Reinaldo Bergamaschi
Mas Antes Disso……Uma Breve Revisao
� Chips
� Fabricacao
� Metodologias de projeto
� Systems-on-Chip – SoCs
� Da Necessidade de Ferramentas de Projeto(CAD tools)
© Reinaldo Bergamaschi
� Invenção do Transistor: 1947-49William Shockley, John Bardeen, Walter BrattainBell Labs (Nobel Prize em 1956)
� Invenção do Circuito Integrado: 1958Jack Kilby – Texas Instruments (Nobel Prize em 2000, c/ Zhores Alferov e Herbert Kroemer)Robert Noyce (TI, depois co-fundador da Intel)
� http://nobelprize.org/educational_games/physics/integrated_circuit/history/index.html
� http://www.pbs.org/transistor/index.html
Chips
© Reinaldo Bergamaschi
Chips: uma breve fotologia
Intel 4004 Intel 8008
Pictures Copyright Intel Corporation (not to scale)
© Reinaldo Bergamaschi
Chips: uma breve fotologia
Intel 8080 Intel 8086
Pictures Copyright Intel Corporation (not to scale)
© Reinaldo Bergamaschi
Chips: uma breve fotologia
Intel 286 Intel 486Intel 386
Pictures Copyright Intel Corporation (not to scale)
© Reinaldo Bergamaschi
Chips: uma breve fotologia
Pentium Core 2 DuoPentium IV
Pictures Copyright Intel Corporation (not to scale)
© Reinaldo Bergamaschi
Chips: uma breve fotologia
IBM Power4 IBM Xenon(XBOX 360)
IBM Cell(Playstation III)
Pictures Copyright IBM Corporation (not to scale)
© Reinaldo Bergamaschi
Power4 : 64-bit PowerPC
� Released 2001
� RISC
Processor
� 170 Milhoes de
Transistores
� 1 GHz
Pictures Copyright IBM Corporation (not to scale)
© Reinaldo Bergamaschi
Freeway: 64-bit S/390 Microprocessador
� Released 2000
� IBM Mainframe
� 47 Milhoes de Trans.
� Tamanho: 17,9 x 9,9 mm
� 1.2 GHz
Pictures Copyright IBM Corporation (not to scale)
© Reinaldo Bergamaschi
Chips: uma breve fotologia
Sun Niagara
Pictures Copyright Sun Corporation (not to scale)
© Reinaldo Bergamaschi
Algebra Booleana
Algebra Normal
Base 10: 0, 1, 2, …, 9
7+ 5
-------12
(Modulo 10)
1 x 101 + 2 x 100 = 12
Algebra Booleana
Base 2: 0, 1
1+ 1
-------10
(Modulo 2)
1 x 21 + 1 x 20 = 2
7 = 1 1 1 = 1 x 22 + 1 x 21 + 1 x 20
5 = 1 0 1 = 1 x 22 + 0 x 21 + 1 x 20+
12 = 1 1 0 0 = 1x 23 + 1 x 22 + 0 x 21 + 0 x 20 = 12
© Reinaldo Bergamaschi
AB
0
1
0 1
Mapa de Karnaugh
Algebra Booleana
Bits
0 == Falso
1 == Verdade
Funcoes Booleanas Basicas
Funcao INV (NOT)
Funcao E ( & )
Funcao OU ( | )
1
00
0
E0 1
1 1 OU
1 0
INV
© Reinaldo Bergamaschi
Claude Shannon
� Um dos principais criadores de toda
esse mundo digital que nos cerca
� Mostrou como a algebra Booleana
pode ser usada para representar o
funcionamento de circuitos eletricos
� Criou a teoria basica das Comunicacoes
ou de como enviar uma mensagem usando BITs
(ele foi o primeiro a usar a palavra BIT)
© Reinaldo Bergamaschi
De Bits ao Transistor
Interruptor
A
110V
B
liga / desliga
CA 0 0 1 1
B 0 1 0 1
C 0 0 0 1
C = A & B
A
B
C
Transistor
CA
B
Porta E
© Reinaldo Bergamaschi
De Funcoes Booleanas ao Chip
Todas as funcoes logicas e aritmeticas podem ser
representadas por conjuntos de funcoes Booleanas
Funcoes Booleanas podem ser implementadas por
conjuntos conectados de Transistores
© Reinaldo Bergamaschi
Photoresist
Mask
Construindo um “bolo” Semicondutor
SiSiliconWafer
SiO2 Si Oxide
UV light
© Reinaldo Bergamaschi
Construindo um “bolo” Semicondutor
SiO2 SiO2SiO2
Si
Development of the exposed photo resist
© Reinaldo Bergamaschi
Construindo um “bolo” Semicondutor
SiO2 SiO2
Si
n+
Difusao ou
implantacao ionica
(Fosforo ou Boro)
© Reinaldo Bergamaschi
Construindo um “bolo” Semicondutor
SiO2 SiO2
Si
n+
Metalizacao
(Aluminio ou Cobre)
© Reinaldo Bergamaschi
Evolução da Tecnologia CMOS
0.5/0.4/0.3/0.11.1 / 0.91.8 / 14045 nm
0.5/0.4/0.3/0.21.2 / 1.01.8 / 1.26065 nm
0.45/0.4/0.35/0.3/0.21.2 / 1.02.2 /1.68090 nm
0.45 /0.35/0.21.221200.13 µm
0.55 / 0.451.83.21800.18 µm
0.552.552500.25 µm
0.63.373500.35 µm
Vt [V]Vdd [V]tox [nm]L [nm]Technology
S G D
n+ n+
L p-
W
tox
From “Nanometer CMOS Ics”, by Harry Veendrick, Springer
© Reinaldo Bergamaschi
Desenhando Milhoes de Transistores
� 1 Transistor ja’ incomoda muita gente
� 1 Milhao incomoda muito mais
� IBM Power4 tem 170 milhoes de transistores
� E’ claro que nao da’ para fazer isso manualmente!
� O que e’ preciso:
Descrever a funcao do chip de um modo mais compacto
Usar “ferramentas de projeto” para automatizar a geracao do
chip
© Reinaldo Bergamaschi
Desenhar um Chip e’ como escrever um Programa
If X == 10 then A = B & C; else A = B | C;
A
=X
10 48 Transistores
A = B & C
&B
C
A = B | C
|B
C
© Reinaldo Bergamaschi
Ferramentas de Projeto
Chip HDL
Sintese Alto Nivel +
Logica
Portas Logicas
Sintese do Layout
Transistores
Sintese das Mascaras
de Fabricacao
Mascaras
Fabricacao
Chip Wafer
© Reinaldo Bergamaschi
Quanto Demora e Quanto Custa?
� MUITO DINHEIRO!
� Cada ferramenta de projeto custa ~60K US$ (usa de 5
a 10 ferramentas x numero de projetistas)
� Cada fabricacao de mascaras pode custar > 1M US$
Quanto mais avancada mais cara (e.g., Copper, SiGe, SOI)
� Power4
Pelo menos 200 pessoas
Pelo menos 2 anos
� Resultado: Algumas centenas de milhoes de dolares (p/
microprocessadores atuais)
© Reinaldo Bergamaschi
Metodologias de Projeto de CIs
Custom
Standard CellsCompiled Cells
Macro Cells
Cell-based
Pre-diffused(Gate Arrays)
Pre-wired(FPGA's)
Array-based
Semicustom
Digital Circuit Implementation Approaches
(c) Giovanni De Micheli
© Giovanni De Micheli
© Reinaldo Bergamaschi
Transição de Custom ao uso de mais automacao e estruturas regulares
Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085
Intel Intel 286286 Intel Intel 486486 Courtesy Intel© Giovanni De Micheli
© Reinaldo Bergamaschi
Design Methodology for Digital ICs
IC Concept and Requirements
System Specification
Technology Dependent
HDL Description
Logical / Electrical Design
• Partitioning,• IP selection,• early analysis
Technology Independent
HDL Description
• High-level synthesis• Logic synthesis• Simulation• Timing analysis
© Reinaldo Bergamaschi
Design Methodology for Digital ICs
Physical / Layout Design
Technology Dependent HDL Description
Mask Fabrication
Wafer Fabrication
Production
• Placement & Routing• Extraction• Timing analysis• Design Rule Check
(DRC)• Electrical Rule Check
(ERC)• Layout vs. Schematic
Check (LVS)
GDSII(layout description)
© Reinaldo Bergamaschi
System-on-Chip (SoC)
� An SoC must contain:Portable / reusable IP
Embedded CPU
Embedded Memory
Real World Interfaces (USB, PCI, Ethernet)
Software (both on-chip and off)
� An SoC may contain:Programmable HW (FPGAs, Flash)
Mixed-signal Blocks
Sensors
� Not just an ASIC !
© Reinaldo Bergamaschi
SoC: IP Cores and Platforms
process (DATA)
variable Temp : integer range 0 to 64;
begin
Temp := 0;
for I in 0 to 63 loop
if (DATA(I) /= '0') then exit;
else Temp := Temp + 1;
end if;
end loop;
COUNT <= Temp;
end process;
SOFT CORES
�Delivered as RTL verilog or VHDL
source code with synthesis scripts
�Customers are responsible for
synthesis, timing closure, and all
front-end processing
© Reinaldo Bergamaschi
SoC: IP Cores and Platforms
FIRM CORES
�Delivered as a netlist to be
included in customer’s netlist (with
don't touch attribute)
�Possibly with placement
information
© Reinaldo Bergamaschi
SoC: IP Cores and Platforms
HARD CORES
�Due to their complexity, they are
provided as a blackbox (GDSII).
Ex. Processors, analog cores,
PLLs
�Usually very tight timing
constraints. Internal views not
alterable or visible by the customer
© Reinaldo Bergamaschi
SoC: IP Cores and Platforms
EBC
HSMC
EMAC3
405 CPU
UIC
HSDMA
PLB-OPB Bridge
PLB Arbiter
OPB 32 bit
MISC MadMal8
PLB 64 bit
DCR bus
IIC
UART0
UART1
GPT
GPIO
PM
ResetCLKG
PLL
OPB Arbiter
PLATFORM-BASED SOC
�Reference HW / SW architecture
that satisfies a set of architectural
constraints, and allows the re-use
of HW and SW components
© Reinaldo Bergamaschi
What is in a Platform: the 405 PBD
EBC
HSMC
EMAC3
405 CPUUIC
HSDMA
PLB-OPB
Bridge
OPB Arb
PLB Arb
OPB 32bit
MISCMadMal8
PLB 64bit
DCR bus
IIC
UART0
UART1
GPT
DCR bus
GPIO
PM
ResetCLKG
PLL
External peripheral bus
- 8-,16-,or
32-bit byte-addressable
- Byte parity on data bus
- 28-bit address bus
- up to 8 banks of ROM,
EPROM, SRAM,Flash &
slave peripheral I/O
- External master support
PC100 SDRAM
- 100MHz memory bus
- 32-bit data bus,
- 13-bit address bus
- 8-bit ECC support
- Four banks
PPC405x3 CPU- 200MHz (WC process 85 °C Tj,2.3V)
- 166MHz (WC process 125 °C Tj,2.3V)
- 16KB instruction cache,8KB data cache
PLB version 3 (64 bit @100MHz)
GPIO- Multiplexed I/O functions
I 2 C interface with
integrated 5V-tolerant
bus transceivers
Two NS 16550-compatible UARTs
General purpose timers
OPB version 1.9,
32 bits @ 50MHz
Ethernet 10/100Mbps - (full-duplex) MAC
- Dedicated Memory Access
Layer (MadMAL) controller
with 50 MHz private bus
High-Speed DMA Controller- Four Int. & Ext. channels
- Scatter/gather capability
- Master on HD serial int.
System clock generation- Single standard PLL
- Sleep control for most cores
- Wake from sleep capability for CPU
© Reinaldo Bergamaschi
How to Design an SoC
SoC MethodologyFirst Contact
Architecture Definition / Die Size Estimation / Package Analysis
Architecture DesignSystem
Specification
Map to Reference Platform
Chip-Level Design and Test
Release to Manufacturing
Embedded Software Design
(doc)
(doc)
(doc)
(doc)
(HDL)
(GDSII)
Chip
Core Library
(HDL)
© Reinaldo Bergamaschi
How to Design an SoC
SoC MethodologyFirst Contact
Architecture Definition / Die Size Estimation / Package Analysis
Architecture DesignSystem
Specification
Map to Reference Platform
Chip-Level Design and Test
Release to Manufacturing
Embedded Software Design
(doc)
(doc)
(doc)
(doc)
(HDL)
(GDSII)
Chip
Core Library
(HDL)
•Architectural sizing•Block Diagram / Chip Function•Die Size estimation•Power Analysis•Early IO Assignment•IP/Cores new or reuse•Possible Risks
© Reinaldo Bergamaschi
How to Design an SoC
SoC MethodologyFirst Contact
Architecture Definition / Die Size Estimation / Package Analysis
Architecture DesignSystem
Specification
Map to Reference Platform
Chip-Level Design and Test
Release to Manufacturing
Embedded Software Design
(doc)
(doc)
(doc)
(doc)
(HDL)
(GDSII)
Chip
Core Library
(HDL)•Is a given Platform appropriate?•Functionality and performance requirements•Include Customer specific requirements•Include High-Level Description of system•Legacy SoC with new requirements•Partition functions between HW and SW
© Reinaldo Bergamaschi
How to Design an SoC
SoC MethodologyFirst Contact
Architecture Definition / Die Size Estimation / Package Analysis
Architecture DesignSystem
Specification
Map to Reference Platform
Chip-Level Design and Test
Release to Manufacturing
Embedded Software Design
(doc)
(doc)
(doc)
(doc)
(HDL)
(GDSII)
Chip
Core Library
(HDL)
•Edit Platform, add/remove cores/logic•Define system parameters•Customize logic•Define Clocks, Resets, Power Mgmt., I/Os
© Reinaldo Bergamaschi
How to Design an SoC
SoC MethodologyFirst Contact
Architecture Definition / Die Size Estimation / Package Analysis
Architecture DesignSystem
Specification
Map to Reference Platform
Chip-Level Design and Test
Release to Manufacturing
Embedded Software Design
(doc)
(doc)
(doc)
(doc)
(HDL)
(GDSII)
Chip
Core Library
(HDL)
•Logic Synthesis•Test Synthesis•Clock Synthesis•Timing Assertions and Analysis•Verification (simulation + formal)•Floorplanning•Detailed Place and Route
© Reinaldo Bergamaschi
How to Design an SoC
SoC MethodologyFirst Contact
Architecture Definition / Die Size Estimation / Package Analysis
Architecture DesignSystem
Specification
Map to Reference Platform
Chip-Level Design and Test
Release to Manufacturing
Embedded Software Design
(doc)
(doc)
(doc)
(doc)
(HDL)
(GDSII)
Chip
Core Library
(HDL)
•HW parameters to header files•Initialization/Boot code•Device drivers•RTOS•Application software
© Reinaldo Bergamaschi
ASIC/SOC Design Tools for Productivity
$1,000,000
$10,000,000
$100,000,000
$1,000,000,000
$10,000,000,000
1990 2000 2010 2020
To
tal
De
sig
n C
os
t
No Automation
Historical
2005 Prediction
$10M
$100M
$1B
$10B
$1M
Advances in Design Automation (DA) have maintained the cost for ASIC designs at a constant level despite significantly increasing complexity
Without Design AutomationAdvances of 1993-2005:$2B vs. $20M Design Cost
Source: ITRS
© Reinaldo Bergamaschi
Raising The Level of Design Abstraction
Realization of design efficiency will require design at a higher level of abstraction
ab
str
act
Transistor-Level
cluster
ab
str
act
Gate-LevelRTL
cluster
ab
str
act
Hardware DescriptionLanguage (HDL)
IP Blocks
cluster
ab
str
act
IP-Level
RTLClusters
SWModels
Time
© Reinaldo Bergamaschi
Para a proxima aula
� Quais as 3 maiores companhias de CAD no mundo? Aonde estao? Quais os seus rendimentos anuais? Quais os seus produtos (ferramentas de CAD) mais rentaveis?
� Metalizacao nos chips era feita de Aluminio. Atualmente e’ quase tudo em Cobre? Quais as principais vantagens do Cobre sobre o Aluminio na metalizacao de chips?
� Quais as companhias no mercado produzindo ferramentas de sintese de alto nivel (e.g., Behavioral synthesis, high-level synthesis, system synthesis)? Quais as linguagens usadas p/ descricao do hardware nessas ferramentas de sintese de alto nivel?
� Baseado no arquivo IntelProcessorHistory.pdf, plotar no mesmo grafico (c/ ano de introducao no eixo X): numero de transistores, frequencia, tecnologia (dimensao minima). (obs, sem plotar os Itaniums)
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