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IC-UNICAMP
MC613 – 2012 1
MC 613
IC/Unicamp
2012s1
Prof Guido Araújo
Prof Mario Côrtes
Registradores e Contadores
IC-UNICAMP
MC613 – 2012 2
Tópicos de Registradores
• Construção usando flip-flops
• Clear assíncrono e Enable
• Registradores deslocamento
• Carga paralela
• Registrador deslocamento universal
• Exemplo de uso em barramento
IC-UNICAMP
MC613 – 2012 3
Registradores
• Conjunto de elementos de memória (flip-flops) utilizados
para armazenar n bits.
• Utilizam em comum os sinais de clock e controle
CLK
D0 D Q
Q
D1
D2
D3
Q0
Q1
Q2
Q3
D Q
Q
D Q
Q
D Q
Q
D Q
Q CLK
D3:0 Q 3:0
IC-UNICAMP
MC613 – 2012 4
8-bit register with asynchronous clear
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY reg8 ISPORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Resetn, Clock: IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END reg8 ;
ARCHITECTURE Behavior OF reg8 ISBEGIN
PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENQ <= "00000000" ;
ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ;END IF ;
END PROCESS ;END Behavior ;
IC-UNICAMP
MC613 – 2012 5
n-bit register with enable
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT (R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock: IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn ISBEGIN
PROCESSBEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Rin = '1' THEN Q <= R ;END IF ;
END PROCESS ;END Behavior ;
IC-UNICAMP
MC613 – 2012 6
Shift Register
t 0
t 1
t 2
t 3
t 4
t 5
t 6
t 7
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
Q 1 Q 2 Q 3 Q 4 Out = In
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
IC-UNICAMP
MC613 – 2012 7
Alternative Shift Register
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;ENTITY shift4 IS
PORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;Clock : IN STD_LOGIC ;L, w : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;END shift4 ;
ARCHITECTURE Behavior OF shift4 IS
BEGINPROCESSBEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF L = '1' THEN Q <= R ;
ELSEQ(0) <= Q(1) ;Q(1) <= Q(2);
Q(2) <= Q(3) ; Q(3) <= w ;
END IF ;END PROCESS ;
END Behavior ;
IC-UNICAMP
MC613 – 2012 8
n-bit left-to-right shift registerLIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY shiftn ISGENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Clock : IN STD_LOGIC ;
L, w: IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftn ;
ARCHITECTURE Behavior OF shiftn ISBEGIN
PROCESSBEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF L = '1' THEN Q <= R ;ELSE
Genbits: FOR i IN 0 TO N-2 LOOPQ(i) <= Q(i+1) ;
END LOOP ;Q(N-1) <= w ;
END IF ;
END PROCESS ;END Behavior ;
IC-UNICAMP
MC613 – 2012 9
Hierarchical code for a
four-bit shift registerLIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY shift4 ISPORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
L, w, Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift4 ;
ARCHITECTURE Structure OF shift4 ISCOMPONENT muxdff
PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC ) ;
END COMPONENT ;BEGIN
Stage3: muxdff PORT MAP ( w, R(3), L, Clock, Q(3) ) ;Stage2: muxdff PORT MAP ( Q(3), R(2), L, Clock, Q(2) ) ;Stage1: muxdff PORT MAP ( Q(2), R(1), L, Clock, Q(1) ) ;Stage0: muxdff PORT MAP ( Q(1), R(0), L, Clock, Q(0) ) ;
END Structure ;
IC-UNICAMP
MC613 – 2012 10
Shift Register com Carga Paralela
Q3 Q2 Q1 Q0
ClockParallel input
Parallel
output
Shift/LoadSerialinput
D Q
Q
D Q
Q
D Q
Q
D Q
Q
IC-UNICAMP
MC613 – 2012 11
Shift Register com Carga ParalelaLIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY lpm ;USE lpm.lpm_components.all ;
ENTITY shift ISPORT ( Clock : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;Shiftin, Load : IN STD_LOGIC ;R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift ;
ARCHITECTURE Structure OF shift ISBEGIN
instance: lpm_shiftregGENERIC MAP (LPM_WIDTH => 4, LPM_DIRECTION =>
"RIGHT")PORT MAP (data => R, clock => Clock, aclr => Reset,
load => Load, shiftin => Shiftin, q => Q ) ;END Structure ;;
IC-UNICAMP
MC613 – 2012 12
Shift Register Universal
• Entrada Serial
– Deslocamento a Esquerda
– Deslocamento a Direita
• Carga Paralela
• Saída Paralela
Exercício:
Diagrama do Shift Register Universal de 4 bits
IC-UNICAMP
MC613 – 2012 13
Registradores em um Barramento
D Q
Q
Clock
D Q
Q
R 1 i n
R 1 o u t
D Q
Q
D Q
Q
R 2 i n
R 2 o u t
Bus
R 1 R 2
IC-UNICAMP
MC613 – 2012 14
Registradores em um Barramento
R1in
Bus
Clock
Control circuit Function
R1 R2 Rk
Data
Extern
R1out
R2in
R2out
Rkin
Rkout
IC-UNICAMP
MC613 – 2012 15
Tópicos de Contadores
• Contadores síncronos e assíncronos
• Contadores de módulo configurável
• Contadores em anel e Johnson
• Preset e Clear síncronos e assíncronos
IC-UNICAMP
MC613 – 2012 16
Contadores síncronos / assíncronos
• Contadores assíncronos
– Entrada de clock dos FFs recebe saída de
estágios anteriores
– Estado do contador: transições dos estágios não
simultâneas (em ripple)
– Circuito mínimo mas requer cuidados com
decodificação
• Contadores síncronos
– Entrada de clock dos FF recebe apenas sinal
externo de clock
– Estado do contador: transições sincronizadas
(razoavelmente simultâneas)
IC-UNICAMP
MC613 – 2012 17
Clock
Q 0
Q 1
Q 2
Count 0 7 6 5 4 3 2 1 0
T Q
Q Clock
T Q
Q
T Q
Q
1
Q 0 Q 1 Q 2
Contador assíncrono: 3 bits DOWN
IC-UNICAMP
MC613 – 2012 18
T Q
Q Clock
T Q
Q
T Q
Q
1
Q 0 Q 1 Q 2
Clock
Q 0
Q 1
Q 2
Count 0 1 2 3 4 5 6 7 0
Contador assíncrono: 3 bits UPAlternativas para UP/DOWN:
• FF sens. borda de descida
• saída = ~Q
IC-UNICAMP
MC613 – 2012 19
0
0
1
1
0
1
0
1
0
1
2
3
0
0
1
0
1
0
4
5
6
1 1 7
0
0
0
0
1
1
1
1
Clock cycle
0 0 8 0
Q 2 Q1 Q0 Q 1 changes
Q 2 changes
Projeto de contador síncrono: 3 bits
IC-UNICAMP
MC613 – 2012 20
Clock
Q 0
Q 1
Q 2
Count 0 1 2 3 5 9 12 14 0
Q 3
4 6 8 7 10 11 13 15 1
T Q
Q Clock
T Q
Q
T Q
Q
1 Q 0 Q 1 Q 2
T Q
Q
Q 3
Contador síncrono: 4 bits
IC-UNICAMP
MC613 – 2012 21
T Q
Q Clock
T Q
Q
Enable
Clear
T Q
Q
T Q
Q
Inclusão de Enable e Clear
Obs: o clear é assíncrono
IC-UNICAMP
MC613 – 2012 22
Contador síncrono com FF D
Clock
Enable D Q
Q
D Q
Q
D Q
Q
D Q
Q
Q0
Q1
Q2
Q3
Outputcarry
IC-UNICAMP
MC613 – 2012 23
Inclusão
de Load EnableD Q
Q
Q 0
D Q
Q
Q 1
D Q
Q
Q 2
D Q
Q
Q 3
D 0
D 1
D 2
D 3
Load
Clock
Outputcarry
0
1
0
1
0
1
0
1
IC-UNICAMP
MC613 – 2012 24
Enable
Q 0 Q 1
Q 2
D 0 D 1
D 2
Load
Clock
1
0
0
0
Clock
Contador mod-6 com Reset síncrono
Obs: o Reset é obtido carregando-se 000 via sinal de load síncrono
0 1 2 3 4 5 0 1
Clock
Count
Q 0
Q 1
Q 2
Ld
IC-UNICAMP
MC613 – 2012 25
Clock
Q 0
Q 1
Q 2
Count 0 1 2 3 4 5 0 1 2
T Q
Q Clock
T Q
Q
T Q
Q
1 Q 0 Q 1 Q 2
Contador mod-5 com Reset assíncrono
Obs: apesar do estado final a ser detectado ser o mesmo do caso anterior,
estado 101 (5), o módulo deste contador é 5 (contagem 0 1 2 3 4 0 1 2 3 4)
IC-UNICAMP
MC613 – 2012 26
EnableQ0Q1Q2
D0D1D2
LoadClock
1000
Clock
Q30 D3
EnableQ0Q1Q2
D0D1D2
LoadClock
000
Q30 D3
BCD0
BCD1
Clear
Contador BCD de 2 dígitos
IC-UNICAMP
MC613 – 2012 27
Contador em anel
D Q
Q
Clock
D Q
Q
D Q
Q
Start
Q 0 Q 1 Q n 1 ”
Contagem p 4 bits: 1000 0100 0010 0001 1000 0100 0010 0001 ....
Módulo?
IC-UNICAMP
MC613 – 2012 28
Contador Johnson
D Q
Q
Clock
D Q
Q
D Q
Q
Q 0
Q 1
Q n 1 –
Reset
Para um contador de 4 estágios:
• Qual é a sequência de contagem
• Qual é o módulo do contador?
IC-UNICAMP
MC613 – 2012 29
Implementação de
contadores em VHDL
IC-UNICAMP
MC613 – 2012 30
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount IS
PORT ( Clock, Resetn, E : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END upcount ;
ARCHITECTURE Behavior OF upcount ISSIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGINPROCESS ( Clock, Resetn )BEGIN
IF Resetn = '0' THENCount <= "0000" ;
ELSIF (Clock'EVENT AND Clock = '1') THENIF E = '1' THEN
Count <= Count + 1 ;ELSE
Count <= Count ;END IF ;
END IF ;END PROCESS ;Q <= Count ;
END Behavior ;
Contador crescente 4 bits
IC-UNICAMP
MC613 – 2012 31
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY upcount ISPORT ( R : IN INTEGER RANGE 0 TO 15 ;
Clock, Resetn, L : IN STD_LOGIC ;Q : BUFFER INTEGER RANGE 0 TO 15 ) ;
END upcount ;
ARCHITECTURE Behavior OF upcount ISBEGIN
PROCESS ( Clock, Resetn )BEGIN
IF Resetn = '0' THENQ <= 0 ;
ELSIF (Clock'EVENT AND Clock = '1') THENIF L = '1' THEN
Q <= R ;ELSE
Q <= Q + 1 ;END IF;
END IF;END PROCESS;
END Behavior;
Contador com LD paralelo, c/ sinais inteiros
Obs: com o uso do tipo BUFFER,
o sinal count não é necessário
IC-UNICAMP
MC613 – 2012 32
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY downcnt ISGENERIC ( modulus : INTEGER := 8 ) ;
PORT ( Clock, L, E : IN STD_LOGIC ;Q : OUT INTEGER RANGE 0 TO modulus-1 ) ;
END downcnt ;
ARCHITECTURE Behavior OF downcnt IS
SIGNAL Count : INTEGER RANGE 0 TO modulus-1 ;BEGIN
PROCESS
BEGINWAIT UNTIL (Clock'EVENT AND Clock = '1') ;
IF E = '1' THENIF L = '1' THEN
Count <= modulus-1 ; -- carrega c móduloELSE
Count <= Count-1 ;
END IF ;END IF ;
END PROCESS;Q <= Count ;
END Behavior ;
Contador decrescente
IC-UNICAMP
MC613 – 2012 33
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;ENTITY upcount IS
PORT ( Clear, Clock: IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;END upcount ;
ARCHITECTURE Behavior OF upcount ISBEGIN
upcount: PROCESS ( Clock )BEGIN
IF (Clock'EVENT AND Clock = '1') THENIF Clear = '1' THEN
Q <= "00" ;ELSE
Q <= Q + '1' ;
END IF ;END IF;
END PROCESS;END Behavior ;
Contador crescente com Reset Síncrono
IC-UNICAMP
MC613 – 2012 34
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;
ENTITY BCDcount IS
PORT ( Clock : IN STD_LOGIC ;Clear, E : IN STD_LOGIC ;
BCD1, BCD0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;END BCDcount ;
Contador BCD de 2 dígitos (entity)
IC-UNICAMP
MC613 – 2012 35
ELSIF E = '1' THEN
IF BCD0 = "1001" THEN
BCD0 <= "0000" ;IF BCD1 = "1001" THEN
BCD1 <= "0000";
ELSEBCD1 <= BCD1 + '1' ;
END IF ;ELSE
BCD0 <= BCD0 + '1' ;END IF ;
END IF ;
END IF;END PROCESS;
END Behavior ;
Contador BCD de 2 dígitos (architect.)ARCHITECTURE Behavior OF BCDcount ISBEGIN
PROCESS ( Clock )BEGIN
IF Clock'EVENT AND Clock = '1' THENIF Clear = '1' THEN
BCD1 <= "0000" ; BCD0 <= "0000" ;
