INSTITUTO DE ELETRÔNICA DE POTÊNCIA

Departamento de Engenharia ElétricaCentro Tecnológico

UNIVERSIDADE FEDERAL DE SANTA CATARINA

Interruptores MOSFET, IGBTs e MCTsPrincipais características para o comando

Textos extraídos de livros, de relatórios internos do INEP e de notas de aplicações daIR e da Motorola:

O transistor IGBT aplicado em eletrônica de Potência - BASCOPÉ, René PastorTorrico; PERIN, Arnaldo José; Editora Sagra Luzzatto, Porto Alegre – RS, 1997.

AN-937 (v.Int)

Gate Drive Characteristics and Requirements forHEXFET®s

Topics covered:Gate drive vs base driveEnhancement vs DepletionN vs P-ChannelMax gate voltageZener diodes on gate?The most important factor in gate drive: the impedance of the gate drive circuitSwitching 101 or Understanding the waveformsWhat happens if gate drive impedance is high? dv/dt induced turn-onCan a TTL gate drive a standard HEXFET®?The universal bufferPower dissipation of the gate drive circuit is seldom a problemCan a C-MOS gate drive a standard HEXFET®?Driving HEXFET®s from linear circuitsDrive circuits not referenced to groundGate drivers with optocouplersGate drive supply developed from the drain of the power deviceGate drivers with pulse transformersGate drivers with choppersDrive requirements of Logic Level HEXFET®sHow fast is a Logic Level HEXFET®driven by a logic circuit?Simple and inexpensive isolated gate drive suppliesA well-kept secret: Photovoltaic generators as gate driversDriving in the MHz? Use resonant gate driversRelated topics

(Note: Most of the gate drive considerations and circuits are equally applicable to IGBTs. Only MOSFETs are mentioned for thesake of simplicity. Special considerations for IGBTs are contained in INT-990)

1. GATE DRIVE VS BASE DRIVE

The conventional bipolartransistor is a current-drivendevice. As illustrated inFigure 1(a). a current mustbe applied between the baseand emitter terminals to pro-duce a flow of current in thecollector. The amount of adrive required to produce agiven output depends uponthe gain, but invariably acurrent must be made to flowinto the base terminal toproduce a flow of current inthe collector.

The HEXFET®is fundamentally different: it is a voltage-controlled power MOSFET device. A voltage must be applied betweenthe gate and source terminals to produce a flow of current in the drain (see Figure 1b). The gate is isolated electrically from thesource by a layer of silicon dioxide. Theoretically, therefore, no current flows into the gate when a DC voltage is applied to it -though in practice there will be an extremely small current, in the order of nanoamperes. With no voltage applied between thegate and source electrodes, the impedance between the drain and source terminals is very high, and only the leakage currentflows in the drain.

IC

IB

CURRENTSOURCE

CURRENTIN BASE

PRODUCESCURRENTIN COLLECTOR

ID

VOLTAGESOURCE

VOLTAGEAT GATE

PRODUCESCURRENTIN DRAIN

+++

(a) Bipolar Transistor (b) HEXFET

Figure 1. Bipolar Transistor is Current Driven, HEXFET is Voltage Driven

AN-936 (v.Int)

The Do's and Don'ts of Using MOS-Gated Transistors(HEXFET® is the trademark for International Rectifier Power MOSFETs)

In this application note, some of the most common do's and don'ts of using power HEXFET®s are described. The objective is tohelp the user get the most out of these remarkable devices, while reducing "on the job" learning time to a minimum.

Topics Covered:Be Mindful of the Reverse Blocking Characteristics of the DeviceBe Careful When Handling and Testing Power HEXFET®sBeware of Unexpected Gate-to-Source Voltage SpikesBeware of Drain or Collector Voltage Spikes Induced by SwitchingDo Not Exceed the Peak Current RatingStay within the Thermal Limits of the DevicePay Attention to Circuit LayoutBe Careful When Using the Integral Body-Drain DiodeBe On Your Gaurd When Comparing Current Ratings

1. BE MINDFUL OF THE REVERSE BLOCKING CHARACTERISTICS OFTHE DEVICE

IGBTs have a limited reverse blocking capability of approximately 20-30 V, with high leakage. This is characterized in IR’s datasheets with a Reverse Avalanche Energy (EARV). This rating isuseful to absorb energy spikes due to the stray inductance inseries with the anti-parallel diode. This is a significantadvantage over bipolar transistors and power darlingtons.A feature of power MOSFETs is that they inherently have builtinto them an integral reverse body-drain diode. The existence ofthis diode is explained by reference to Figure 1. When thesource terminal is made positive with respect to the drain,current can flow through the middle of the source cell, across aforward biased P-N junction. In the "reverse" direction, thepower HEXFET® thus behaves like a P-N junction rectifier. Theintegral body-drain diode is a real circuit element, and itscurrent handling capability is typically as high as that of thetransistor itself. Some circuits require an "inverse" rectifier to beconnected across the switching device, and in these circuits itwill often be possible to utilize the body-drain diode of theHEXFET® provided the proper precautions are taken.

2. BE CAREFUL WHEN HANDLING & TESTING POWER HEXFET®S

The user's first "contact" with a MOS-gated transistor could be a package of parts arriving on his desk. Even at this stage, itbehooves one to be knowledgeable about some elementary precautions. Being MOS devices, HEXFET®s can be damaged by staticcharge when handling, testing or installing into a circuit. Power Devices have large input capacitance, and are able to absorbstatic charge without excessive buildup of voltage. In order to avoid possible problems, however, the following procedures shouldbe followed as a matter of good practice, wherever possible:

• MOS-gated transistors should be left in their anti-static shipping bags, or conductive foam, or they should be placed in metalcontainers or conductive tote bins, until required for testing or connection into a circuit. The person handling the deviceshould ideally be grounded through a suitable wrist strap, though in reality this added precaution is seldom essential.

• Devices should be handled by the package, not by the leads. When checking the electrical characteristics of the MOS-gatedtransistors on a curve tracer, or in a test circuit, the following precautions should be observed:

• Test stations should use electrically conductive floor and table mats that are grounded. Suitable mats are availablecommercially.

Figure 1. Basic HEXFET Structure

AN-936 (v.Int)• When inserting the device in a curve tracer or a test circuit, voltage should not be applied until all terminals are solidly

connected into the circuit.• When using a curve tracer, a resistor should be connected in series with the gate to damp spurious oscillations that can

otherwise occur on the trace. A suitable value of resistance is 100 ohms.• For repeated testing, it is convenient to build this resistor into the test fixture.• When switching from one test range to another, voltage and current settings should be reduced to zero, to avoid the

generation of potentially destructive voltage surges during switching. The next step is to connect the device into an actual circuit. The following simple precautions should be observed: • Work stations should use electrically grounded table and floor mats.• Soldering irons should be grounded.

Now that the device has been connected into its circuit, it is ready for the power to be applied. From here on, success in applyingthe device becomes a matter of the integrity of the circuit design, and of what circuit precautions have been taken to guardagainst unintentional abuse of its ratings.

The following are the interrelated device and circuit considerations that lead to reliable, trouble-free design.

3. BEWARE OF UNEXPECTED GATE-TO-SOURCE VOLTAGE SPIKES

Excessive voltage will punch through the gate-source oxide layer and result in permanent damage. This seems obvious enough,but it is not so obvious that transient gate-to-source overvoltages can be generated that are quite unrelated to, and well in excessof, the amplitude of the applied drive signal. The problem is illustrated by reference to Figure 2.If we assume that the impedance, Z, of the drive source is high, then any positive-going change of voltage applied across thedrain and source terminals (caused, for example, by the switching of another device in the circuit) will be reflected as a positive-going voltage transient across the source and the drain terminals, in the approximate ratio of:

The above ratio is typically about 1 to 6. This means that a change of drain-to-source voltage of 300V, for example, couldproduce a voltage transient approaching 50V between the gate and source terminals. In practice this “aiming” voltage will notappear on the gate if the dv/dt is positive because the MOS-gated device goes in conduction at approximately Vgs = 4V, therebyclamping the dv/dt at the expense of a current transient and increased power dissipation. However, a negative-going dv/dt willnot be clamped. This calculation is based upon the worst case assumption that the transient impedance of the drive circuit is highby comparison with the gate-to-source capacitance of the device. This situation can, in fact, be quite easily approximated if thegate drive circuit contains inductance—for example the leakage inductance of an isolating drive transformer. This inductanceexhibits a high impedance for short transients, and effectively decouples the gate from its drive circuit for the duration of thetransient.

The negative-going gate-to-source voltage transient produced under the above circumstances may exceed the gate voltage ratingof the device, causing permanent damage. It is, of course, true that since the applied drain transient results in a voltage at thegate which tends to turn the device ON, the overall effect is to an extent self-limiting so far as the gate voltage transient isconcerned. Whether this self-limiting action will prevent the voltage transient at the gate from exceeding the gate-source voltagerating of the device depends upon the impedance of the external circuit. Spurious turn-on is of itself undesirable, of course,though in practical terms one may grudgingly be able to accept this circuit operating imperfection, provided the safe operatingarea of the device is not violated.

Notice that a voltage clamp (a conventional zener diode is suitable for this purpose) to prevent the gate-source voltage ratingfrom being exceeded will not prevent the dv/dt induced turn-on, as the gate will not reach the zener voltage. In many instancesthe zener is responsible for generating oscillations in the gate circuit, particularly when a significant amount of stray inductanceis present. A more fundamental solution, of course, is to make the impedance of the gate circuit low enough that not only is thegate-source voltage rating not exceeded, but also the voltage transient at the gate is contained to a level at which spurious turn-ondoes not occur.

1

1+C

C

gs

dg

AN-936 (v.Int)

It should be remembered that a collapse of voltage across the device (i.e., a negative-going dv/dt) will produce a transientnegative voltage spike across the gate-source terminals. In this case, of course, there will be no tendency for the device to turnON, and hence no tendency for the effect to be self-limiting. A zener diode connected to clamp positive transients willautomatically clamp negative-going transients, limiting them to the forward conduction voltage drop of the zener.

"POSITIVEGOING"CHANGE

"NEGATIVE GOING"CHANGE

DRAIN-SOURCEVOLTAGE

WITH NOCLAMPING GATE-SOURCE

VOLTAGE

WITH NOCLAMPING

D

CDS

CDG

CGS

S

ZG

DRIVESOURCE

IMPEDANCE

EXTERNALLY CONNECTEDCLAMPING ZENER DIODE

Figure 2. A Rapidly Changing Applied Drain-Source Voltage will Produce Gate-Source Transients

R

L

+E

(a) UNCLAMPEDINDUCTIVE

LOAD

OVERVOLTAGETRANSIENTDUE TO L

Figure 3. Drain-Source Overvoltage Transient whenSwitching Off with Unclamped Inductive Load

+E

LS

LS

R

L

LSD

S

VDS

E(b) CLAMPEDINDUCTIVE

LOAD

OVERVOLTAGETRANSIENTDUE TO LS

LS = STRAY CIRCUITINDUCTANCE

Figure 4. Drain-Source Overvoltage TransientProduced by Stray Circuit Inductance When Switching

Off with Clamped, Inductive Load

AN-936 (v.Int)

4. BEWARE OF DRAIN OR COLLECTOR VOLTAGE SPIKES INDUCED BYSWITCHING

The uninitiated designer is often not aware that self-inflicted overvoltage transients can be produced when the device is switchedOFF, even though the DC supply voltage for the drain circuit is well below the VDS rating of the transistor.Figure 3 shows how a voltage spike is produced when switching the device OFF, as a result of inductance in the circuit. Thefaster the device is switched, the higher the overvoltage will be.Inductance is always present to some extent in a practical circuit, and therefore, there is always danger of inducing overvoltagetransients when switching OFF. Usually, of course, the main inductive component of the load will be "clamped", as shown inFigure 4. Stray circuit inductance still exists, however, and overvoltage transients will still be produced as a result—to saynothing of the fact that the clamping diode may not provide an instantaneous clamping action, due to its "forward recovery"characteristic.

The first approach to this problem is to minimize stray circuit inductance, by means of careful attention to circuit layout, to thepoint that whatever residual inductance is left in the circuit can be tolerated. HEXFET®s have an inductive energy rating thatmakes capable of withstanding these inductive spikes, assuming that the data sheet limits for energy and temperature are notviolated. IGBTs, however, do not have an avalanche rating, and a clamping device should be connected, physically as close aspossible to the drain and source terminals, as shown in Figure 5. A conventional zener diode, or a "transorb" clamping device,are satisfactory for this purpose. An alternative clamping circuit is shown in Figure 6, depending on the voltage and currentrating of the circuit. The capacitor C is a reservoir capacitor and charges to a substantially constant voltage, while the resistor R is sized to dissipatethe "clamping energy" while maintaining the desired voltage across the capacitor. The diode D must be chosen so that its forwardrecovery characteristic does not significantly spoil the transient clamping action of the circuit. A simple RC snubber can also beused, as shown in Figure 7. Note, however, that an RC snubber not only limits the peak voltage, it also slows down the effectiveswitching speed. In so doing, it absorbs energy during the whole of the switching period, not just at the end of it, as does avoltage clamp. A snubber is therefore less efficient than a true voltage clamping device.

Note that the highest voltage transient occurs when switching the highest level of current. The waveform of the voltage across thedevice should be checked with a high-speed oscilloscope at the full load condition to ensure that switching voltage transients arewithin safe limits.

5. DO NOT EXCEED THE PEAKCURRENT RATING

All power transistors have a specified maximum peakcurrent rating. This is conservatively set at a level thatguarantees reliable operation and it should not beexceeded. It is often overlooked that, in a practicalcircuit, peak transient currents can be obtained that arewell in excess of the expected normal operating current,unless proper precautions are taken. Heating, lightingand motor loads, for example, consume high in-rushcurrents if not properly controlled. A technique thatensures that the peak current does not exceed thecapability of the device is to use a current sensing controlthat switches it OFF whenever the currentinstantaneously reaches a preset limit.

Unexpectedly high transient current can also be obtainedas a result of rectifier reverse recovery, when a transistoris switched ON rapidly into a conducting rectifier. This isillustrated in Figure 8. The solution is to use a fasterrectifier, or to slow down the switching of the transistorto limit the peak reverse recovery current of the rectifier.

6. STAY WITHIN THE THERMAL LIMITS

+E

LS

LSR

L

LSVDS

D

S CLAMPINGZENER

OVERVOLTAGETRANSIENTCLAMPEDBY ZENER

(c) CLAMPEDINDUCTIVE LOADWITH LOCAL D-SZENER CLAMP

Figure 5. Overvoltage Transient at Switch-Off Clamped byLocal Drain-Source Zener

AN-936 (v.Int)

Power transistors are thermally limited. They must bemounted on a heatsink that is adequate to keep thejunction temperature within the rated under the"worst case" condition of maximum power dissipationand maximum ambient temperature.

It must be remembered that in a switchingapplication, the total power is due to the conductionlosses and the switching loss. Switching time andswitching losses of HEXFET®s are essentiallyindependent of temperature, but the conduction lossesincrease with increasing temperature, because RDS(on)

increases with temperature. IGBTs, on the contrary,have switching losses that highly dependent oftemperature, while conduction losses are not. Thismust be taken into account when sizing the heatsink.The required thermal resistance of the heatsink canbe calculated as follows:The transistor conduction power, PT, is given

approximately by PT = On-state Voltage x Drain orCollector currentThe switching energy depends upon the voltage andcurrent being switched and the type of load. The totalswitching loss, PS, is the total switching energy, εT,

multiplied by the operating frequency, f. eT is the sumof the energies due to the individual switchings thattake place in each fundamental operating cycle:

PS = εT f

The total power dissipation is the sum of the conduction power, PT, and the switching power, PS.

P = PT + PS

Since:∆TJA = PRth

where:Rth = junction-to-ambient thermal

resistance

The junction-to-ambient thermal resistance, RJA,is made up of the internal junction-to-casethermal resistance, RJC, plus the case-to-

heatsink thermal resistance, RCS, plus the sink-

to-ambient thermal resistance, RSA. The firsttwo terms are fixed for the device, and therequired thermal resistance of the heatsink, RS-

A, for a given junction temperature rise DTJ-A,can be calculated from:

RS-A = RJ-A - (RJC + RC-S)

7. PAY ATTENTION TO CIRCUIT LAYOUT

+E

E

EC

D

R

C

EC

0

Figure 6. Overvoltage Transient at Switch-Off Limited byLocal Clamp

+ELS

LSR

L

LS

D

S

(d) CLAMPED INDUCTIVELOAD WITH LOCAL

D-S SNUBBER

VDS

SNUBBER

OVERVOLTAGE TRANSIENTREDUCED BY SNUBBER

E

Figure 7 . Overvoltage Transient at Switch-Off Limited by LocalCapacitor-Resistor Snubber

AN-936 (v.Int)

Stray inductance in the circuit can cause overvoltage transients, slowing down of the switching speed, unexpected unbalance ofcurrent between parallel connected devices, and unwanted oscillations.

In order to minimize these effects, stray circuit inductance must be minimized. This is done by keeping conduction paths as shortas possible, by minimizing the area of current loops, by using twisted pairs of leads, and by using ground plane construction.Local decoupling capacitors alleviate the affects of any residual circuit inductance, once these measures have been taken.Circuit layout should be kept as symmetrical as possible in order to maintain balanced currents in parallel connected HEXFET®sor IGBTs. The gates of parallel connected devices should be decoupled by small ferrite beads placed over the gate connections, orby individual resistors in series with each gate. These measures prevent parasitic oscillations.

8. BE CAREFUL WHEN USING THE INTEGRAL BODY-DRAIN DIODE

The HEXFET®'s integral body-drain diode exhibitsminority carrier reverse recovery. Reverse recovery pre-sents a potential problem when switching any rectifier off;the slower the rectifier, the greater the problem. Bycomparison with the HEXFET® itself, the switching speedof the integral reverse rectifier is quite slow. The switchingspeed of a circuit which utilizes the body-drain diode of theHEXFET® may therefore be limited by the rectifier.Whether this will be so depends upon the circuit and theoperating conditions.

Regardless of the overall circuit configuration, or theparticular application, the "local" circuit operatingsituation that is troublesome occurs when the freewheelingcurrent from an inductive load is commutated from theintegral rectifier of one HEXFET® to the transistor of an"opposite" HEXFET®, the two devices forming a tandemseries connected pair across a low impedance voltagesource, as shown in Figure 8. This “local” circuitconfiguration occurs in most chopper and inverterschemes.

If the incoming HEXFET® switches ON too rapidly, thepeak reverse recovery current of the integral body-draindiode of the opposite HEXFET® will rise too rapidly, thepeak reverse recovery current rating will be exceeded, andthe device may possibly be destroyed.

The peak reverse recovery current of the rectifier can be reduced by slowing down the rate of change of current during thecommutation process. The rate of change of current can be controlled by purposefully slowing down the rate of rise of the gatedriving pulse. Using this technique, the peak current can be reduced to almost any desired extent, at the expense of prolongingthe high dissipation switching period.

The oscillograms in Figure 9 illustrate the effect. By slowing the total switch-ON time from 300ns to 1.8ms, the peak current ofthe IRF330 has been decreased from 20A to 10A. The energy dissipation associated with the “unrestrained” switch-ON in Figure9(a) is 0.9mJ, whereas it is 2.7mJ for the controlled switch-ON of Figure 9(b).

Note also that it is not necessary to slow the switching-OFF of the HEXFET®, hence the energy dissipation at switch-OFF will berelatively small by comparison with that at switch-ON. For operation at frequencies up to a few kHz, where ultra-fast switching isnot mandatory, slowing the applied gate drive signal to reduce the peak reverse recovery current of the "opposite" rectifier offersa good practical solution.

I

IIF:INDUCTIVE LOADCURRENT ISFREE-WHEELINGIN THEBODY-DRAINDIODE OFTHIS DEVICE

THEN:

TAKE CARE WHENSWITCHING-ONTHIS DEVICE

Figure 8. Local Circuit Configuration and OperatingCondition Requiring Special Care When Using the

HEXFET's Integral Body-Drain Diode.

AN-936 (v.Int)

9. BE ON YOUR GUARD WHEN COMPARING CURRENT RATINGS

The user can be forgiven if he assumes that the continuous drain current rating, that appears on the data sheet represents thecurrent at which the device can actually be operated continuously in a practical system. To be sure, that's what it shouldrepresent; unfortunately it often does not.

Frequently a "continuous" current rating is assigned to the device which in practical terms cannot be used, because the resultingconduction power dissipation would be so large as to require a heatsink with an impractically low thermal resistance, and/or animpractically low ambient operating temperature. The best advice to the user is to compare different types on the basis of hightemperature conduction and switching losses, and not of current rating. For MOSFETS, it is sufficient to compare RDS(on) at 25°C, and this provides a common basis for comparison. This parameter, taken in conjunction with the junction-case thermalresistance, is a much better indication of the power MOSFET true current handling capability.

10mV 2µµS10mV 2µµS

100V

(a) I(max) = 20A, di/dt = 50A/ms.Switching time = 300nsec.

(b) I(max) = 20A, di/dt = 50A /µ/µs.Switching time = 1.8 ms..

Figure 9. Oscillograms of IRF330 Switching into Reverse Rectifier of Another IRF330 with FreewheelingCurrent of 4A.

Top Trace: Voltage 100V/div.Bottom Trace: Current 4A/div.

Time Scale: 2ms/div.

AN-937 (v.Int)

When a voltage is applied between the gate andsource terminals, an electric field is set up within theHEXFET®. This field “inverts” the channel (Figure2) from P to N, so that a current can flow from drainto source in an uninterrupted sequence of N-typesilicon (drain-channel-source). Field-effecttransistors can be of two types: enhancement modeand depletion mode. Enhancement-mode devicesneed a gate voltage of the same sign as the drainvoltage in order to pass current.

Depletion-mode devices are naturally on and areturned off by a gate voltage of the same polarity asthe drain voltage. All HEXFET®s are enhancement-mode devices.

All MOSFET voltages are referenced to the sourceterminal. An N-Channel device, like an NPNtransistor, has a drain voltage that is positive withrespect to the source. Being enhancement-modedevices, they will be turned on by a positive voltageon the gate. The opposite is true for P-Channeldevices, that are similar to PNP transistors.Although it is common knowledge that HEXFET®transistors are more easily driven than bipolars, a few basic considerationshave to be kept in mind in order to avoid a loss in performance or outright device failure.

2. GATE VOLTAGE LIMITATIONS

Figure 2 shows the basic HEXFET®structure. The silicon oxide layer between the gate and the source regions can be puncturedby exceeding its dielectric strength. The data sheet rating for the gate-to-source voltage is between 10 and 30 V for mostHEXFET®s.Care should be exercised not to exceed the gate-to-source maximum voltage rating. Even if the applied gate voltage is kept belowthe maximum rated gate voltage, the stray inductance of the gate connection, coupled with the gate capacitance, may generateringing voltages that could lead to the destruction of the oxide layer. Overvoltages can also be coupled through the drain-gateself-capacitance due to transients in the drain circuit. A gate drive circuit with very low impedance insures that the gate voltageis not exceeded in normal operation. This is explained in more detail in the next section.

Zeners are frequently used “to protect the gate from transients”. Unfortunately they also contribute to oscillations and have beenknown to cause device failures. A transient can get to the gate from the drive side or from the drain side. In either case, it wouldbe an indication of a more fundamental problem: a high impedance drive circuit. A zener would compound this problem, ratherthan solving it. Sometimes a zener is added to reduce the ringing generated by the leakage of a gate drive transformer, incombination with the input capacitance of the MOSFET. If this is necessary, it is advisable to insert a small series resistor (5-10Ohms) between the zener and the gate, to prevent oscillations.

3. THE IMPEDANCE OF THE GATE CIRCUIT

To turn on a power MOSFET a certain charge has to be supplied to the gate to raise it to the desired voltage, whether in thelinear region, or in the “saturation” (fully enhanced) region. The best way to achieve this is by means of a voltage source, capableof supplying any amount of current in the shortest possible time. If the device is operated as a switch, a large transient currentcapability of the drive circuit reduces the time spent in the linear region, thereby reducing the switching losses.

On the other hand, if the device is operated in the linear mode, a large current from the gate drive circuit minimizes therelevance of the Miller effect, improving the bandwidth of the stage and reducing the harmonic distortion. This can be betterunderstood by analyzing the basic switching waveforms at turn-on and turn-off for a clamped inductive load, as shown in Figures

DRAIN DRAIN

DIODE CURRENT

TRANSISTORCURRENT

TRANSISTORCURRENT

NSOURCE

NGATE OXIDE

P

N

INSULATINGOXIDE

SOURCEMETALLIZATION

SILICON GATECHANNEL

Figure 2. Basic HEXFET Structure

AN-937 (v.Int)

3 and 5. Figure 3 shows the waveforms of the drain current, drain-to-source voltage and gate voltage during the turn-on interval.For the sake of simplicity, the equivalent impedance of the drive circuit has been assumed as purely resistive.

At time, t0, the drive pulse starts to rise. At t0 it reaches the threshold voltage of the HEXFET®s and the drain current starts toincrease. At this point, two things happen which make the gate-source voltage waveform deviate from its original “path”. First,inductance in series with the source which is common to the gate circuit (“common source inductance”) develops an inducedvoltage as a result of the increasing source current. This voltage counteracts the applied gate drive voltage, and slows down therate of rise of voltage appearing directly across the gate and source terminals; this in turn slows down the rate of rise of thesource current. This is a negative feedback effect: increasing current in the source produces a counteractive voltage at the gate,which tends to resist the change of current.

The second factor that influences the gate-source voltage is the so called “Miller” effect. During the period t1 to t2 some voltageis dropped across “unclamped” stray circuit inductance in series with the drain, and the drain-source voltage starts to fall. The

LOAD

"OPEN CIRCUIT"DRIVEPULSE

DRIVE CIRCUITRESISTANCE

G

INDUCTANCESTRAY

SOURCESOURCEINDUCTANCE

DRAIN-SOURCEVOLTAGE

DRAIN-SOURCE

VTH

"OPEN CIRCUIT" DRIVE PULSE

GATE-SOURCEVOLTAGE

I

t0 t1 t3t2 t4

Figure 3. Waveforms at Turn-On

DRIVE

+

- ID

+

-IS

THIS INDUCED VOLTAGESUBSTRACTS FROM THEDRIVE VOLTAGERESULTING IN

RESULTING INTHIS VOLTAGE RISING

MORE SLOWLYRESULTING IN

SLOW RISE OF IS

VOLTAGE DROP ACROSSTHIS L MEANS THAT THE

DRAIN VOLTAGE FALLRESULTING IN

DISCHARGE OFTHIS CAPACITOR

RESULTING INMORE CURRENT

THROUGH THISRESISTANCE

Figure 4. Diagrammatic Representation of EffectsWhen Switching-ON

DRAIN-SOURCEVOLTAGE

G-S VOLTAGE

CURRENT

GATE VOLTAGEGIVING IVTH

"OPEN CIRCUIT"DRIVE PULSE

t4t3t2t1t0

I

Figure 5. Waveforms at Turn-OFF

AN-937 (v.Int)

decreasing drain-source voltage is reflected across the drain-gate capacitance, pulling a discharge current through it, andincreasing the effective capacitive load on the drive circuit.This in turn increases the voltage drop across the source impedance of the drive circuit, and decreases the rate of rise of voltageappearing between the gate and source terminals. Obviously, the lower the impedance of the gate drive circuit, the less this effectwill be. This also is a negative feedback effect; increasing current in the drain results in a fall of drain-to-source voltage, which inturn slows down the rise of gate-source voltage, and tends to resist the increase of drain current. These effects are illustrateddiagramatically in Figure 4. This state of affairs continues throughout the period t1 to t2, as the current in the HEXFET®rises to

the level of the current, IM, already flowing in the freewheeling rectifier, and it continues into the next period, t2 to t3, when thefreewheeling rectifier goes into reverse recovery.

Finally, at time t3 the freewheeling rectifier starts to support voltage and drain current and voltage start to fall. The rate of fall ofdrain voltage is now governed almost exclusively by the Miller effect, and an equilibrium condition is reached, under which thedrain voltage falls at just the rate necessary for the voltage between gate and source terminals to satisfy the level of drain currentestab-lished by the load. This is why the gate-to-source voltage falls as the recovery current of the freewheeling rectifier falls,then stays constant at a level corresponding to the drain current, while the drain voltage falls. Obviously, the lower the impe-dance of the gate-drive circuit, the higher the discharge current through the drain-gate self-capacitance, the faster will be the falltime of the drain voltage and the switchinglosses.

Finally, at time t4, the HEXFET®is switched fullyon, and the gate-to-source voltage rises rapidlytowards the applied “open circuit” value.

Similar considerations apply to the turn-offinterval. Figure 5 shows theoretical waveformsfor the HEXFET®in the circuit of Figure 4 duringthe turn-off interval. At to the gate drive starts to

fall until, at tl , the gate voltage reaches a levelthat just sustains the drain current and the deviceenters the linear mode of operation. The drain-to-source voltage now starts to rise. The Millereffect governs the rate-of-rise of drain voltageand holds the gate-to-source voltage at a levelcorresponding to the constant drain current.Once again, the lower the impedance of the drivecircuit, the greater the charging current into thedrain-gate capacitance, and the faster will be therise time of the drain voltage. At t3 the rise ofdrain voltage is complete, and the gate voltageand drain current start to fall at a rate determinedby the gate-source circuit impedance.

We have seen how and why a low gate driveimpedance is important to achieve highswitching performance. However, even whenswitching performance is of no great concern, itis important to minimize the impedance in thegate drive circuit to clamp unwanted voltagetransients on the gate. With reference to Figure6, when one HEXFET®is turned on or off, a stepof voltage is applied between drain and source ofthe other device on the same leg. This step ofvoltage is coupled to the gate through the gate-to-drain capacitance, and it can be large enough toturn the device on for a short instant (“dv/dtinduced turn-on”). A low gate drive impedance would keep the voltage coupled to the gate below the threshold.

A STEP OF VOLTAGE CAUSES

VDS Q1

VDS Q2

VGS Q1

VGS Q2

A TRANSIENTON THE GATE

Figure 6. Transients of Voltage Induced on the Gate by RapidChanges on the Drain-to-Source Voltage

AN-937 (v.Int)

In summary: MOS-gated transistors should be driven from low impedance (voltage) sources, not only to reduce switching losses,but to avoid dv/dt induced turn-on and reduce the susceptibility to noise.

4. DRIVING STANDARD HEXFET®S FROM TTL

Table 1 shows the guaranteed sourcing and sinking currents for different TTL families at their respective voltages. From thistable, taking as an example of the 74LS series, it is apparent that, even with a sourcing current as low as 0.4 mA, the guaranteedlogic one voltage is 2.4V (2.7 for 74LS and 74S). This is lower than the possible threshold of a HEXFET®. The use of a pull-upresistor in the output, as shown in Figure 7, takes the drive voltage up to 5 V, as necessary to drive the gate of Logic LevelHEXFET®s, but is not sufficient to fully enhance standard HEXFET®s. Section 8 covers the drive characteristics of the logiclevel devices in detail.

LogicConditions 54 / 74 54H / 74H

(54L) /74L

(54LS) /74LS 74S

Logic ZeroMin. sink current

for VOL

16mA< 0.4V

20mA< (0.4V) /

20mA< (0.3V) /

0.4V

(4) / 8< (0.4V) /

0.5V

20mA

0.5V

Logic OneMax. source

current for VOH

-0.4mA>2.4V

-0.5mA>2.4V

-0.2mA>2.4V

-0.4mA> (2.5) /

2.7V

-1.0mA>2.7V

Typical GatePropagation Delay

10ns 7ns 50ns 12ns 4ns

Table 1. Driving HEXFET®s from TTL (Totem Pole Outputs)

Open collector buffers, like the 7406, 7407, etc., possibly withseveral drivers connected in parallel as shown in Figure 9, giveenough voltage to drive standard devices into “fullenhancement”, i.e. data sheet on-resistance. The impedance ofthis drive circuit, however, gives relative long switching times.Whenever better switching performance is required, interfacecircuits should be added to provide fast current sourcing andsinking to the gate capacitances. One simple interface circuit isthe complementary source-follower stage shown in Figure 9. Todrive a MOSFET with a gate charge of 60 nC in 60 ns an averagegate current of 1 A has to be supplied by the gate drive circuit, asindicated in INT-944. The on-resistance of the gate driveMOSFETs has to be low enough to support the desired switchingtimes.

With a gate charge of 60 nC and at a switching frequency is100kHz, the power lost in the gate drive circuit is approximately:

P = VGS x QG x f = 12 x 60 x 10-9 x 100 x 103 = 72mW

The driver devices must be capable of supplying 1A withoutsignificant voltage drop, but hardly any power is dissipated inthem.

5. DRIVING STANDARD HEXFET®S FROM C-MOS

While the same general considerations presented above for TTL would also apply to C-MOS, there are three substantialdifferences that should be kept in mind:

1. C-MOS has a more balanced source/sink characteristic that, on a first approximation, can be thought of as a 500 ohmresistance for operation over 8V and a 1k ohm for operation under 8V (Table 2).

Figure 7. Direct Drive from TTL Output

LOAD

VH

PULL-UPRESISTOR

TTL(TOTEM POLE)

AN-937 (v.Int)

2. C-MOS can operate from higher supply voltages than 5V so that HEXFET®saturation can be guaranteed.3. Switching times are longer than those for TTL (Table 2).

When C-MOS outputs are directly coupled to the gate ofa HEXFET®, the dominant limitation to performance isnot the switching time, but the internal impedance(assuming that C-MOS are operated from a 10V orhigher voltage supply). It will certainly not be able toturn OFF the HEXFET®as fast as the TTL, while theturn-ON waveform will be slightly better than what canbe achieved with a 7407 with a 680 ohm pull-upresistor. Of course, gates can be paralleled in anynumber to lower the impedance and this makes C-MOSa very simple and convenient means of drivingHEXFET®s. Drivers can also be used, like the 4049 and4050 which have a much higher current sinkingcapability (Table 2), but they do not yield any significantimprovement in current sourcing.

For better switching speeds, buffer circuits, like the oneshown in Figure 9, should be considered, not only toprovide better current sourcing and sinking capability,but also to improve over the switching times of the C-MOS output itself and the dv/dt noise immunity.

6. DRIVING HEXFET®S FROM LINEAR CIRCUITS

The complementary source follower configuration of Figure 9 can also be used in linear applications to improve drive capabilityfrom an opamp or other analog source.

Most operational amplifiers have a very limited slew rate, in the order of few V/microsec. This would limit the bandwidth to lessthan 25kHz. A larger bandwidth can be obtained with better operational amplifiers followed by a current booster, like the onesshown in Figures 10 or 11. For a system bandwidth of 1MHz, the opamp bandwidth must be significantly higher than 1MHz andits slew rate at least 30V/µs.

VH

680 ΩΩ

IRF320

7407

680 ΩΩ

12V

Figure 8. High Voltage TTL driver and its waveforms

Figure 9. Simple Interface to Drive HEXFETs from TTL

7407

1K

VH

LOAD+12V

INPUT

87

2

4

5 6

1

3

IRF7307 OR IRF7507

AN-937 (v.Int)

Standard BufferedOutputs 4049 / 4050 Drivers

Logic Supply Voltage

Logic Conditions 5V 10V 15V 5V 10V 15VLogic Zero:Approximate sink currentfor VOL < 1.5V

1.5mA 3.5mA 4mA 20mA 40mA 40mA

Logic One:Minimum source current for VOH

-0.5mA> 4.6V

-13mA> 9.5V

-3.4mA> 13.5V

-1.25mA> 2.5V

-1.25mA> 9.5V

-3.75mA> 13.5V

Typical switching times of logic drive signals:RISEFALL

100ns100ns

50ns50ns

40ns40ns

100ns40ns

50ns20ns

40ns15ns

Table 2. Driving HEXFET®s from C-MOS (Buffered)

When analog signals determine the switching frequency orduty cycle of a HEXFET®, as in PWM applications, avoltage comparator is normally used to command theswitching. Here, too, the limiting factors are the slew rate ofthe comparator and its current drive capability. Responsetimes under 40ns can be obtained at the price of low outputvoltage swing (TTL compatible). Once again, the use ofoutput buffers like the ones shown in Figures 9, may benecessary to improve drive capability and dv/dt immunity. Ifbetter switching speeds are desired. a fast op-amp should beused.

In many applications, when the HEXFET®is turned on,current transfers from a freewheeling diode into theHEXFET®. If the switching speed is high and the strayinductances in the diode path are small, this transfer canoccur in such a short time as to cause a reverse recoverycurrent in the diode high enough to short out the dc bus. Forthis reason, it may be necessary to slow down the turn-on ofthe HEXFET®while leaving the turn-off as fast as practical.Low impedance pulse shaping circuits can be used for thispurpose, like the ones in Figures 12 and 13.

7. DRIVE CIRCUITS NOTREFERENCED TO GROUND

To drive a HEXFET®into saturation, an appropriate voltagemust be applied between the gate and source. If the load isconnected between source and ground, and the drive voltage isapplied between gate and ground, the effective voltage betweengate and source decreases as the device turns on. An equilibriumpoint is reached in which the amount of current flowing in theload is such that the voltage between gate and source maintainsthat amount of drain current and no more. Under theseconditions the voltage drop across the MOSFET is certainlyhigher than the threshold voltage and the power dissipation canbe very high. For this reason, the gate drive circuit is normallyreferenced to the source rather than to the ground. There are

Figure 10. Dual Supply Op-Amp Drive Circuit

VH

LOAD

+12V

INPUTS

87

2

4

5 6

1

3

IRF7309 OR IRF7509

-

+

-12V0.1 µµFCER

FETINPUT

OPAMP

Figure 11. Single Supply Op-Amp Drive Circuit(Voltage Follower)

CA3103

VH

LOAD

+12V

87

2

4

5 6

1

3

IRF7307 OR IRF7507

-

+

0.1 µµFCER

FETINPUT

OP AMP.

2

3

AN-937 (v.Int)

basically three ways of developing a gate drive signal that is referenced to a floating point:

1. By means of optically coupled isolators.2. By means of pulse transformers.

By means of DC to DC chopper circuits with transformer isolation.

7.1 MGDs with optocouplers

Most optocouplers require a separatesupply grounded to the source on thereceiving end of the optical link anda booster stage at the output, asshown in Figure 14a. One of themajor difficulties encountered in theuse of optocouplers is theirsusceptibility to noise. This is ofparticular relevance in applicationswhere high currents are beingswitched rapidly. Because of thedv/dt seen by the VEE pin, theoptocoupler needs to be rated forhigh dv/dt, in the order of 10 V/ns.

Figure 15a shows an MGD withunder-voltage lockout and negativegate bias. When powered with a 19V floating source, the gate drivevoltage swings between +15V and -3.9V. D1 and R2 offset the emitter voltage by 3.9V. The switching waveforms shown in Figure 15b are similar to those in Figure14b except for the negative bias. Q3, D2 and R5 form the under voltage lockout circuit.

The LED D2 is used as low voltage, low current reference diode. Q3 turns on when the voltage at the anode of D2 exceeds thesum of the forward voltage of LED and the base-emitter voltage of Q3. This enables the operation of the optocoupler. Thetripping point of the under voltage lock-out circuit is 17.5V. The start-up wave forms are shown in Figure 16.

Figure 12. A pulse shaper. The 555 is used as an illustration of a Schmitt Trigger pulse shaper

INPUT PULSE

T = RC

WITH DIODECONNECTEDAS SHOWN

VH

LOAD

+12V

87

2

4

5 6

1

3

IRF7307 OR IRF7507

C

555

8

42

36

1 R

4.7K

INPUT

Figure 13. Pulse shaper implemented with an integrator

VH

LOAD

+12V

87

2

4

5 6

1

3

C

INPUTCA3103-

+

C

R

VINPUT

WITH DIODECONNECTEDAS SHOWN

SLOPE OF VRC V/SEC

AN-937 (v.Int)

The auxiliary supply for the optocoupler and its associated circuitry can be developed from the drain voltage of the MOSFETitself, as shown in Figure 17, 18 and 19. This supply can be used in conjunction with the UV-lockout shown in Figure 15 toprovide a simple high-quality optoisolated drive.

The circuit in Figure 17a can be modified to provide higheroutput current. By changing C1 to 680pF and R3 to 5.6k, itsperformance changes to what is shown in Figures 20, 21 and22. Other methods of developing isolated supplies are discussedin Section 9.

7.2 Pulse transformers

A pulse transformer is, in principle, a simple, reliable andhighly noise-immune method of providing isolated gate drive.Unfortunately it has many limitations that must be overcomewith additional components. A transformer can only transfer tothe secondary the AC component of the input signal.Consequently, their output voltage swings from negative topositive by an amount that changes with the duty cycle, asshown in Figure 23. As a stand-alone component they can beused for duty cycles between 35 and 65%.

Figure 14a. Simple high current optoisolated driver

87

2

4

5 6

1

3

+ C210

BATT115V

GATE

EMITTER3.9V

C10.1

IRF7307 OR IRF7507

VCC

OUT

EN

VEEC

A8

7

6

5

ISO1R1 2

3

3.3k

Input: 5V/div

Output : 5V/div

Horiz: 500ns/div

Figure 14b: Waveforms associated with thecircuit of Figure 14a when loaded with 100nF

Figure 15a: Optoisolated driver with UV lockout and negative gate bias

87

2

4

5 6

1

3C210

BATT119V

GATE

EMITTER

3.9V

C10.1

IRF7309 OR IRF7509

VCC

OUT

EN

VEEC

A8

7

6

5

ISO1R1 2

3

3.3k

R310k

Q3R5

R41K

D2LED

R54.7K

1K D13.9V

C310

HCPL2200 2N2222

UNDERVOLTAGELOCK-OUT

OUTPUTBUFFER

SINGLE TO SPLITPOWER SUPPLY

IN+

IN-

AN-937 (v.Int)

Input: 5V/div

Output : 5V/div

Horiz: 500ns/divFigure 15b: Waveforms of the circuit in Figure 21a

when loaded with 100nF

FILE: 01A-POL.DAT

VBATT1 5V/div

Output: 5V/div

Horiz: 20ms/div File: 01-UV.datFigure 16. Start-up waveforms for the

circuit of Figure 15a.

Gate Voltage: 10V/div

C2 ripple voltage: 0.5V/div

Q1 drain voltage: 200V/div

Horiz: 5 µµs/div File: GPS-1.plt

Figure 17b. Waveforms of the circuit in Figure23a.C1 = 100 pF, R3 = 5.6 k, f = 50 kHz

Figure 17a. Drive supply developed from the drain voltage

+15V

D315V

15VRTN

C20.1

R3D2

1N4148C1R2

100D1

1N4148

Q1IRF840

R1

10

Q2IRF840R4

RG2

DRVRTN

DRIVE

VCC(300V)

20 30 40 50 60 70 80 90 1000

1

2

3

Frequency (kHz)

Zen

er C

urre

nt (

mA

)

Figure 18 . Zener current (max output current)for the circuit in Figure 23a.

Figure 19 . Start-up voltage at 50 kHzfor the circuit in Figure 23a.

Horiz.: 500 µµs/div File: GPS-3.PLT

C2 voltage: 5V/div.

AN-937 (v.Int)

They have the additional advantage of providing a negative gate bias. One additional limitation of pulse transformers is the factthat the gate drive impedance is seriously degraded by the leakage inductance of the transformer. Best results are normallyobtained with a few turns of twisted AWG30 wire-wrap wire on a small ferrite core.

Lower gate drive impedance and a wider duty-cycle range can be obtained with the circuit in Figure 24a. In this circuit, Q1 andQ2 (a single Micro-8 package) are used to buffer the input and drive the primary of the transformer. The complementary MOSoutput stage insures low output impedance and performs wave shaping. The output stage is fed by a dc restorer made by C2 andD1 that references the signal to the positive rail. D1 and D2 are also used to generate the gate drive voltage.

The input and output wave form with 1nF load capacitance are shown in Figure 24b. The turn-on and turn-off delays are 50ns.The rise and fall times are determined by the 10 Ohm resistor and the capacitive load. This circuit will operate reliably between20 and 500 kHz, with on/off times from 0.5 to 15 microsecs.

Due to the lack of an under voltage lock-out feature, the power-up and power down behavior of the circuit is important.Intentionally C1 and C2 are much bigger in value then C3 so that the voltage across C3 rises to an adequate level during the firstincoming pulse. The power-up wave forms at 50kHz switching frequency and 50% duty cycle are shown in Figure 25. Duringthe first pulse, the output voltage is 10V only, and drops back below 10V at the fifth pulse.

Gate voltage: 10V/div.

Drain voltage: 200V/div.

C2 ripple voltage: 1V/div

Horiz: 2 µµs/div File: gps-4.plt

Figure 20. Waveforms of the circuit inFigure 23a. with C1=680pF, R3=1k,

f=100kHz.

10 20 30 40 50 60 70 80 100Frequency (kHz)

Zen

er C

urre

nt (

mA

)

Figure 21 . Zener current (max output current)for the circuit in Figure 23a.with C1 = 680pF, R3 = 1k

20

10

0

90

C2 voltage: 5V/div

Horiz: 100 µµs/div. File: GPS-6.plt

Figure 22. Start-up voltage at 100 kHz for thecircuit in Figure 23a. with C1=680pF, R3=R3=1k

0VGS

Figure 23. Volt-seconds acrosswinding must balance

AN-937 (v.Int)

8

2

4

5 6

1

3

+12V

IN

12VRTN

Q2IR7509

Q1IR7509

C1

1

T1C2

1

D1IN4148

D2

IN4148

1

Q3

2

3R2

10

R1

10Q4

1

3

2C40.1

IN

100K

E

G

1nLOAD

R3

IRFL014 OR IRFD014T1: CORE: 331X1853E2A A1=2600 (PHILIPS, OD=0.625", Ae=0.153CM^2)

PRIMARY: 17T, SEC.: 27T

Figure 24a. Improving the performance of a gate drive transformer

Figure 24b. Waveforms associated with the circuitof Figure 24a

Input: 5V/div.

Output: 5V/div.

HORIZ: 50µµS/div. FILE: X2-START.PLT

Figure 25. Waveforms during start-up for the circuit inFigure 24a.

87

2

4

5 6

1

3

+12V

12VRTN

INPUT

C1

0.1

C1

0.47

T1

1

C2

VCC

IN

FAULT

VSCOM

CS

87

65

U21

4

IR2127/8

HO

VB

2

3

R38.2K

D5

11DF6

R21K

C

G

R4220

C510n

E

D411DQ04

100K

T1: CORE: 331X185 3E2A, A1=2600 (OD=0.625", Ae=0.153 CM^2)PRIMARY: 17T, AWG 28 SEC: 27T, AWG 28

Figure 26a. Transformer-coupled MGD with UV lockout and short-circuit protection

AN-937 (v.Int)

The power down of the circuit is smooth and free from voltage spikes. When the pulse train is interrupted at the input, the C2capacitor keeps the input of the CMOS inverter high and R1 discharges C3. By the time the input to the CMOS inverter dropsbelow the threshold voltage of Q4, C3 is completely discharged the output remains low.

The addition of a MOS-Gate Driver IC improves the performance of the circuit in Figure 24a, at the expenses of prop delay. Thecircuit shown in Figure 26a has the following features:

- No secondary supply required- Propagation delay ~500ns (CL= 10nF)- Duty cycle range 5% to 85%- Nominal operating frequency 50kHz (20kHz to 100kHz)- Short circuit protection with Vce sensing. Threshold Vce = 7.5V- Undervoltage lock-out at Vcc = 9.5V- Over voltage lock out at Vcc = 20V

The short circuit protection is implemented with a Vce sensing circuit in combination with the current sense input (CS) ofIR2127/8. When the HO pin if U2 goes high R3 starts charging C5. Meanwhile the IGBT turns on, the collector voltage drops tothe saturation level, D5 goes into conduction and C5 discharges. When the collector voltage is high, D5 is reverse biased and thevoltage on C5 keeps raising. When C5 voltage exceeds 250mV the IR2127/8 shuts down the output. The fault to shut-downdelay is approximately 2 microsecs.

For operation with a large duty cycle, several options are available. The circuits described in AN-950 use a saturating transformerto transfer the drive charge to the gate. The circuit shown in Figure 28a, on the other hand, achieves operation over a wide rangeof duty cycles by using the MGD as a latch. It has the following features:

- Frequency range from DC to 900kHz.- Turn-on delay: 250ns.- Turn-off delay 200ns- Duty cycle range from 1% to 99% at 100kHz.- Under voltage and over voltage lockout.- Optional short circuit protection, as shown in Figure 26a

In the circuit of Figure 28a the transformer is small (8 turns), since it transmits only short pulses to the secondary side. TheMGD on the secondary side of the transformer is latched by the feedback resistor R4. Figures 28b and 28c show the performanceof this circuit at the two extremes of 900 kHz and 2.5 Hz

Horiz.: 500ns/div.

Output: 5V/div.

Input: 2V/div.

Figure 26b. Waveforms associated with thecircuit of Figure 26a.

Input: 5V/div.

Output: 5V/div.

IR2121 ERR pin: 5V/div.

Horiz: 1 µµs/div. FILE: X1-ERR.PLT

Figure 27. Shutdown due to high VCEsat

AN-937 (v.Int)

7.2 Chopping gate drives

Chopper circuits can maintain a gate drive signal for an indefinite period of time, have good noise immunity performance and,with some additional circuitry, the isolated supply can be avoided.

The basic operating principle is shown in Figure 29. To turn on the MOSFET, a burst of high frequency is transmitted to thesecondary side. The MOSFET is turned off by interrupting the high frequency. The diode and the bipolar transistor form acrowbar that rapidly discharges the gate.

In addition to providing the gate drive signal, the high frequency transformer is frequently used to power auxiliary circuitry, likeshort-circuit protection, thus avoiding a dedicated supply.

8. DRIVE REQUIREMENTS AND SWITCHING CHARACTERISTICS OFLOGIC LEVEL HEXFET®S

Many applications require a power MOSFET to be driven directly from 5 V logic circuitry. The on-resistance of standard powerMOSFETs is specified at 10 V gate drive, and are generally not suitable for direct interfacing to 5V logic unless an oversizedMOSFET is employed.

87

2

4

5 6

1

3

+12V

12VRTN

IN

C1

1

C2

1nF

T14.7K

R2VCC

IN

ERR

VSVSS

CS

87

65

U11

4

IR2121

HO

VB

2

3

R4 18K

R5 18K

+15V

G

C31

E

TRANSFORMER: CORE: 266CT125-3E2A, (OD=0.325", Ae=0.072cm,^2, A1=2135)

PRIMARY: 8T, AWG 28 SEC: 8T, AWG 28

Figure 28a. Transformer-coupled MGD for operation from DC to 900 kHz

R1560

R318K 15VRTN

IRF7509 OR IRF7309

Input: 2V/div.

Output: 25.ns/div.

Horiz.: 25.ns/div. File: XP-900K.PLT

Figure 28b. Waveforms associated with thecircuit of Figure 28a operated at 900 kHz

Input: 5V/div.

Output: 10V/div.

Reference 60Hz: 10V/div.

Horiz: 50ms/div. File: XP-2P5HZ.PLT

Figure 28c. Waveforms associated with the circuitof Figure 28a operated at 2.5 Hz

AN-937 (v.Int)

Logic level HEXFET®s are specifically designed for operation from 5V logic and have guaranteed on-resistance at 5 or 4.5 Vgate voltage. Some have guaranteed on-resistance at 2.7 V.

Some important considerations for driving logic level HEXFET®s are discussed in this section and typical switching performanceof these is illustrated when driven by some common logic drive circuits.

8.1 Comparison to Standard HEXFET®s

Some devices are available as Logic-level HEXFET®s as well as standard HEXFET®s. The logic-level version uses a thinner gateoxide and different doping concentrations. This has the following effects on the input characteristics:

• Gate Threshold voltage is lower.• Transconductance is higher.• Input capacitance is higher.• Gate-source breakdown voltage is lower.

While input characteristics are different, reverse transfer capacitance, on-resistance, drain-source breakdown voltage, avalancheenergy rating, and output capacitance are all essentially the same. Table 3 summarizes the essential comparisons betweenstandard and logic level HEXFET®s.

Characteristics and Ratings Standard HEXFET ®

(IRF Series)Comparable Logic Level HEXFET ®

(IRL Series)Gate Threshold Voltage VGS(on) 2 - 4V 1 - 2V

On-Resistance RDS(on)

Logic level HEXFET®has same value of RDS(on)

VGS = 5V as standard HEXFET®at VGS = 10V

RDS(on) of logic level HEXFET®also speed at VGS = 4VTransconductance gfs Typically 39% larger for logic level HEXFET®

Input Capacitance Crs Typically 33% larger for logic level HEXFET®

Output Capacitance Crss Essentially the sameReverse Transfer Capacitance Crss Essentially the sameGate Charge

Gate-Source Qgs Essentially the sameGate-Drain Qgd Essentially the sameTotal Qg Essentially same as

VGS = 10VEssentially same atVGS = 5V

Drain Source BreakdownVoltage

BVDSS Same

Continuous Drain Current ID Same

Single Pulse Avalanche EnergyEAS Same

Max. Gate-Source Voltage VGS + 20V +10V

Table 3: Essential Comparisons of Standard and Logic Level HEXFET®s

The gate charge for full enhancement of the logic level HEXFET®is, however, about the same as for a standardHEXFET®because the higher input capacitance is counteracted by lower threshold voltage and higher transconductance. Sincethe logic level HEXFET®needs only one half the gate voltage, the drive energy is only about one half of that needed for thestandard HEXFET®. Since the gate voltage is halved, the gate drive resistance needed to deliver the gate charge in a given timeis also halved, relative to a standard HEXFET®. In other words, for the same switching speed as a standard HEXFET®powerMOSFET, the drive circuit impedance for the logic level HEXFET®must be approximately halved.

The equivalence of switching times at one half the gate resistance for the logic level HEXFET®is illustrated by the typicalswitching times for the IRL540 and the IRF540 HEXFET®s shown in Table 4, using data sheet test conditions.

AN-937 (v.Int)

Gate Resistance Gate Voltage Drain Current Typical Values (ns)RG

(ΩΩ)VGS

(V)ID

(A)tD on tr tD on tr

9 10 28 15 72 40 504.5 5 28 15 72 44 56

Table 4: Typical Resistive Switching Times for IRL540 and IRF540

TTL families do not actually deliver 5V in their VOH condition, even into an open circuit. The 5V level can, however, be reachedby the addition of a pull-up resistor from the output pin to the 5V bus, as illustrated in Figure 30. Without the pull-up resistor,the RDS(on) value at VGS = 5V may not be attained, and the value specified at VGS = 4V should be used for worst case design.

8.2 Driving Logic Level HEXFET®s

The gate threshold voltage of MOSFETs decreases with temperature. At high temperature it can approach the VOL(max)

specification of the logic driver. Care should be exercised to insure that VTH(min) at the highest operating temperature is greaterthan VOL(max) of the various logic families in order to guarantee complete turn off.

55574 8

328 5

15 VCONTROL

INPUT

470LOAD

Figure 29.

+5V

LOGICINPUTS

RET

LOAD

Figure 30. Pull-up resistor usedto deliver 5V gate drive

+VDD

R1

Figure 31a. High common mode inductance

RL

D

LD

G

LS

S

LW

RET.SIG. RET.

DRIVE

+VDD

R1

Figure 31b. Minimum common modeinductance

RL

D

LD

G

LS

S

LWRET.SIG. RET.

AN-937 (v.Int)

Common source inductance plays a significant role in switching performance. In the circuit of Figure 31a the switchingperformance is degraded due to the fact that VGS is reduced by (LS + LW) di/dt, where di/dt is the rate of change of the drain

current. By eliminating LW from the drive circuit, VGS can approach the applied drive voltage because only LS (the internalsource inductance) is common.

This can be done by separately connecting the power return and the drive signal return to the source pin of the switchingHEXFET®, as shown in Figure 31b. Thus, the load current ID does not flow through any of the external wiring of the drivecircuit; consequently, only the internal source inductance LS is common to both load and drive circuits.

In the case of logic level HEXFET®s, for which VGS is 5V and not 10V, the loss of drive voltage due to common mode

inductance has proportionately twice the effect as it would on a 10V drive signal, even though actual values of LS and LW are thesame.

8.3 Resistive Switching Tests

In the following tests of switching performance, the physical layout of the test circuit was carefully executed so to minimize thecommon source inductance. The following precautions were also observed:

1. RL was built by paralleling 0.5W resistors to achieve the desired load resistance (see Table 5).

2. To minimize inductance in the load circuit, a 10 µF low-ESR low-ESL capacitor was connected directly from +VDD to thesource of the DUT.

3. To provide a low source impedance for the 5V gate pulse of the DUT, a 0.1 µF low-ESR low-ESL capacitor was connecteddirectly between pin 14 and pin 7 of the driver IC.

4. To provide minimum common source impedance, the source of the DUT was the common return point of all ac and dcsystem grounds.

5. To reduce stray inductances and thus achieve maximum switching speeds, the physical size of the high current loop (RL,DUT, 10 µF) was reduced to the smallest practical limits.

Only the 5 volt families have been tested as logic level HEXFET®drives: bipolar and CMOS (and their derivatives), as indicatedbelow.

TTL GATES

DM7400N: Standard TTL74F00PC: High Speed TTLDM74S00N: Schottky TTLDM74LS00N: Low Power Schottky TTLDM74AS00N: Advanced Schottky TTL

+VDD = 0.5 BVDSS

Figure 32. Switching test circuit. Logic level driver is one-quarter of a quadNAND gate.

RL

DUT

+5V

0.1pF0.1pF

3

15

12

7, 4, 5, 910, 12, 13

50 ΩΩ

VSS

+5V0 SIG. GEN.

SCOPE

AN-937 (v.Int)

CMOS GATES

74AC00PC: Advanced CMOS74ACT00PC: TTL Compatible CMOSMM74HC00N: Micro CMOSMM74HCT00N: TTL Compatible Micro CMOS

BIPOLARDS0026: High Speed MOSFET Driver

The test conditions for the resistive switching performance is shown in Table 5. The resistive switching times obtained with theabove TTL and CMOS gates are tabulated in Table 6. In this table ton = Time in microseconds from 90% to 10% VDD and toff =

Time in microseconds from 10% to 90% VDD. Inductive switching gives faster voltage rise times than resistive switching due tothe resonant charging of the output capacitance of the device. Voltage fall times are essentially the same.

LOGIC LEVELHEXFET®

SWITCHINGVOLTAGE

(V)

SWITCHING CURRENT(A)

RDSON(ΩΩ)

RL(ΩΩ)

IRLZ14IRLZ24IRLZ34IRLZ44IRLZ514IRLZ524IRLZ524IRLZ544

3030303050505050

8162440581225

0.240.120.060.0340.600.300.180.085

3.251.51.20.79.55.94.01.9

Table 5. Resistive Switching Conditions

Logic Family Logic Level HEXFET ®,Quad, Dual Input IRLZ14 IRLZ24 IRLZ34 IRLZ44 IRL514 IRL524 IRL534 IRL544

Nand Gate ton toff ton toff ton toff ton toff ton toff ton toff ton toff ton toffDM7400NSTANDARD TTL 0.173 0.018 0.663 0.026 0.700 0.076 1.491 0.146 0.151 0.0220.238 0.041 0.263 0.060 0.616 0.124

7400FDOPCHIGH SPEED TTL 0.124 0.008 0.490 0.013 0.429 0.068 0.863 0.146 0.104 0.0040.159 0.034 0.176 0.059 0.372 0.136

DM7400SCHOTTKY TTL 0.133 0.092 0.549 0.020 0.503 0.032 1.068 0.142 0.116 0.0060.183 0.041 0.212 0.057 0.441 0.132

DM74LSLOW POWER SCHOTTKY TTL 0.174 0.038 0.778 0.093 0.706 0.146 1.438 0.342 0.155 0.0400.240 0.062 0.267 0.090 0.567 0.199

DM4SDONADVANCED SCHOTTKY TTL 0.126 0.008 0.567 0.013 0.446 0.023 0.896 0.149 0.111 0.0050.161 0.127 0.176 0.058 0.336 0.130

74ACOOPCADVANCED CMOS 0.012 0.007 0.120 0.012 0.125 0.027 0.251 0.139 0.036 0.0040.052 0.028 0.066 0.055 0.125 0.125

74ACTOOPCTTL COMPATIBLE CMOS 0.012 0.006 0.121 0.011 0.125 0.016 0.233 0.127 0.033 0.0440.052 0.027 0.060 0.055 0.120 0.122

MM74CHCOONMICRO CMOS 0.066 0.039 0.179 0.091 0.227 0.147 0.508 0.328 0.058 0.0440.092 0.068 0.111 0.096 0.232 0.213

MM74HCTCO4TTL COMPATIBLE MICRO CMOS 0.066 0.030 0.179 0.060 0.227 0.123 0.504 0.269 0.068 0.0350.092 0.051 0.111 0.086 0.232 0.186

DS0026HIGH SPEED MOSFET DRIVER 0.052 0.005 0.016 0.005 0.014 0.007 0.032 0.016 0.021 0.0040.036 0.004 0.036 0.005 0.029 0.009

Table 6. Results of the resistive load switching test

Typical Test Oscillograms

IRLZ24: 60V, 0.1 Ohm, N-Channel, TO-220 logic level HEXFET®was driven by each of the logic families listed in Table 4 andthe comparative resistive switching times photographed.

AN-937 (v.Int)

9. SIMPLE AND INEXPENSIVE METHODS TO GENERATE ISOLATEDGATE DRIVE SUPPLIES.In several applications, dc-to-dc converters are used to power the MOS Gate Driver. Although the gate drive requires littlepower, the noisy environment, the isolation voltage and creepage distance requirements and the high dv/dt between the primaryand secondary size make the design of the DC-to-DC converter somewhat complicated. Its key parameters are listed below:OUTPUT VOLTAGE, CURRENT. The output voltage of the DC-to-DC converter is the sum of the positive and negative drivevoltage to the gate. The load current required from the DC-to-DC converter is the sum of the current consumption of the drivecircuit and the average drive current to the gate.

dv/dt CAPABILITY. When the DC-DC converter powers a high sideswitch, the secondary side of theconverter is connected to the output ofthe power circuit. The rapid change ofhigh voltage at the output of powercircuit stresses the isolation of thetransformer and injects noise to theprimary side of the transformer.Switching noise at the primary sidedisturbs the operation of the converterand the control circuit for the powerstage, causing false triggering andshoot-through. Therefore atransformer with high voltageisolation, appropriate creepagedistances and low winding-to-winding capacitance is required in thisapplication.

SMALL SIZE. To reduce the interwinding capacitances the transformer must be made small. This implies operation at highfrequency. Small size and compact layout help reducing the EMI and RFI generated by the converter. Figure 33a shows aforward converter made with two CD4093 gates to generate the clock and drive the MOSFET. Energy as transferred to thesecondary when the MOSFET is on, in about 33% of the cycle. When the MOSFET is off, the secondary winding is used todemagnetize the transformer and transfer the magnetizing energy to the load, thus eliminating the need for a demagnetizingwinding. The switching waveforms are shown in Figure 33b. The ringing in the drain voltage during the fly-back period is due tothe loose coupling between the primary and the secondary windings. The load current vs. output voltage characteristic of thecircuit is shown in Figure 34. When the output current falls below 5 mA, the circuit works as flyback converter because thedemagnetizing current flows through the output. A minimum load of 5mA is required to limit the output voltage at 15V.

+12V

Figure 33a. 100 kHz Forward converter

1312

11 100

1µµF

IRFD110

1N414812K

20K

56

4

CD40931n

12VRTN

1µµF

T1

4XIN4148 V0

RL

f = 100kHz

T1 TRANSFORMER: DORE: PHILIPS 240XT250-3EA2 TOROID

(OD = 0.75", Ae=0.148CM^2, AI=3000)

PRIMARY: 14 TURNS, AWG 30 TEFLON INSULATED WIRE

SECONDARY: 24 TURNS, AWG 30 TEFLON INSULATED WIRE

Gate voltage: 5V/div.

Drain voltage: 10V/div.

Horiz: 2 µµs/div.

Figure 33b. Waveforms associated with thecircuit in Figure 33a

35

30

25

20

15

100 20 40 60 80 100 120

Load current (mA)

Out

put V

olta

ge (

V)

Figure 34. Load current vs. output voltage at 100 kHz,Rout = 27.7 Ohms

AN-937 (v.Int)

If the converter is loaded with aconstant and predictable load, a zenercan provide the necessary regulation.Otherwise a three-terminal regulatoror a small zener-driven MOSFET maybe necessary.The circuit in Figure 35a is similar tothe previous one, except that thehigher switching frequency is higher(500 kHz) and the transformer issmaller. The remaining three gates inthe package are connected in parallelto drive the MOSFET and reduce theswitching losses. The switchingwaveforms are shown in Figure 35b.The output resistance (Rout) of thiscircuit is higher than the circuit shownin Figure 33a, mainly because thestray inductance of the smaller transformer is higher and the effects of the stray inductance are higher. Figure 37a shows a push-pull operated at 500 kHz. The single gate oscillator produces a 50% duty cycle output, while the remaining gates in the packageare used to drive the push-pull output stage. The primary of the transformer sees half the voltage compared to the previouscircuit, therefore the number of turns at the primary were reduced to half.

10. PHOTOVOLTAIC GENERATORS AS GATE DRIVERS

A photovoltaic generator is a solid state power supply powered by light, normally an LED. The combination of the LED and thephotovoltaic generator in one package is called a Photovoltaic Isolator or PVI and is available in a 8-pin DIP package. As avoltage source, the PVI can function as a “dc transformer” by providing an isolated low current to a load. While an optoisolatorrequires a bias supply to transmit a signal across a galvanic barrier, the PVI actually transmits the energy across the barrier.More information on the PVI can be found in Application Note GBAN-PVI-1 which appears in the Microelectronic RelayDesigner’ s Manual. This data book also contains the data sheet for the photovoltaic isolator, the PVI1050. A circuit is alsoprovided in the AN to significantly speed up turn off of the switch. As a gate driver the PVI has significant limitations: its shortcircuit current is in the order of 30 microA with a very high internal impedance. Its simplicity, however, makes it appealing insolid-state relay replacements, where switching times are not important and switching transients are not present.

A typical application is the ac switch described below. The IGBT and the power MOSFET are not suited to switching ACwaveforms directly. The IGBT can only conduct current in one direction while the power MOSFET has an anti-parallel diodethat will conduct during every negative half-cycle. Bidirectional blocking capability can be achieved by connecting two powerMOSFETs source to source, or two IGBTs with anti-parallel diodes emitter to emitter, as shown in Figure 39.

+12V

Figure 35a. 500 kHz Forward converter

13

1211

100

1µµF

IRFD110

1N41481K

6K

56

4

CD4093220p

12VRTN

1µµF

T1

4XIN4148 V0

RL

f = 500kHz

T1: CORE: PHILIPS 266CT125-3E2A (od=0.375", Ae=0.072CM^2, AL=2135

PRIMARY: 4T, AWG 30, SECONDARY: 7T, AWG30

9

810

1

23

14

7

30

25

20

15

10

0 10 20 30 5040Load current (mA)

Out

put v

olta

ge (

V)

Figure 36. Load current vs. output voltage,Rout = 27.7 Ohms

Drain Voltage: 10V/div.

Gate voltage: 5V/div.

Horiz.: 250ns/div.

Figure 35b. Waveforms associated with thecircuit in Figure 35a

AN-937 (v.Int)

In the case of the MOSFET, there is the possibility that, for low current levels, the current flows through both MOSFETchannels, instead that one MOSFETs and diode, thereby achieving lower overall voltage drop. The MOSFET channel is abidirectional switch, that is, it can conduct current in the reverse direction.

If the voltage across the MOSFETchannel is less than the VF of theintrinsic diode (which typically has ahigher VF than discrete diodes), thenthe majority of the current will flowthrough the MOSFET channelinstead of the intrinsic diode. Thegate drive for both the MOSFETs andIGBTs must be referenced to thecommon sources or emitters of thedevices. Since this node will beswinging with the AC waveform, anisolated drive is necessary. The PVIcan be used, as shown in Figure 40.

11. RESONANT GATE DRIVE TECHNIQUES

As indicated in Section 14, gate drive losses in hard switching areequal to Qgs x Vgs x f. An IRF630 operated at 10 Mhz with agate voltage of 12 V would have gate drive losses of 3.6 W,independent from the value of the gate drive resistor. Clearly, toachieve hard switching at this frequency, the resistance of the gatedrive circuit is limited to whatever is associated with the internalimpedance of the driver and with the gate structure of the deviceitself. Furthermore, the stray inductance of the gate drive circuitmust be limited to tens of nH. The design and layout of such acircuit is not an easy task.

An alternative method to drive the gate in such an application isto design a resonant circuit that makes use of the gate capacitanceand stray inductance as its reactive components, adding whateverinductance is necessary to achieve resonance at the desiredfrequency. This method can reduce the peak of the gate drivecurrent and losses in half, while simplifying the design of the gatedrive circuit itself. Since the gate charge is not dissipated at everyswitching transition, but stored in a reactive component, the gatedrive losses are proportional to the resistance of the gate drivecircuit, rather than being independent from it. More informationon this gate drive method can be found in an article by El-Hamamsy: Design of High-Efficiency RF Class-D PowerAmplifier and in references at the end of this article (IEEETransactions on Power Electronics, May 1994, page 297).

Related Topics

MOS-Gate Driver IcsTransformer drive with wide duty cycle capabilityGate ChargeThree-phase MOS-Gate DriverPhotovoltaic Isolators (PVI)

+12V

Figure 37a. 500 kHz Forward converter

13

1211

100

1µµF10K

56

4

CD4093220p

12VRTN

1µµFT1

1N4148 V0

RL

f = 500kHz

T1: CORE: PHILIPS 266CT125-3E2A (od=0.375", Ae=0.072CM^2, AL=2135

PRIMARY: 4T, AWG 30, SECONDARY: 7T, AWG30

9

810

1

23

14

7

7, 8

2

4

5, 6

13

7T

1N4148

100nF100nF

2TIRF7307

Buffer input: 5V/div.

Buffer Output: 5V/div.

Horiz.: 500ns/div

Figure 37b. Waveforms associated with the circuit in Figure 37a

20

19

18

17

16

15

14

130 10 20 30 40 50 60

Figure 38. Load current vs. output voltage,Rout=27.7 Ohms

AN-944 (v.Int)

Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs

Topics covered:

• Background• Test method• How to interpret the gate charge curve• How to estimate switching times• How to compare different devices

1. Input behavior of a MOS-gated transistor

Designers unfamiliar with MOSFET or IGBT input characteristics begin drive circuit design by determining component valuesbased on the gate-to-source, or input, capacitance listed on the data sheet. RC value based on the gate-to-source capacitancenormally lead to a gate drive that is hopelessly inadequate. Although the gate-to-source capacitance is an important value, the gate-to-drain capacitance is actually more significant—andmore difficult to deal with—because it is a non-linear capacitance affected as a function of voltage; the gate-to-source capacitanceis also affected as a voltage function, but to a much lesser extent. This gate-to-drain capacitance function is similar to that foundin vacuum tube amplifiers.

The gate-to-drain capacitance effect is akin to the “Miller” effect, a phenomenon by which a feedback path between the inputand output of an electronic device is provided by the interelectrode capacitance. This affects the total input admittance of thedevice which results in the total dynamic input capacitance generally being greater than the sum of the static electrodecapacitances. The phenomenon of the effects of the plate impedance and voltage gain on the input admittance was first studied invacuum tube triode amplifier circuits by John M. Miller. Essentially, at high frequencies where the grid-to-plate (gate-to-drain)capacitance is not negligible, the circuit is not open but involves a capacitance that is a function of the voltage gain. Solving forthe "Miller" effect is not exactly a straightforward process, even with vacuum tubes where much is known, but is even moredifficult in MOSFETs. In actuality, the gate-to-drain capacitance though smaller in static value than the gate-to-sourcecapacitance, goes through a voltage excursion that is often more than 20 times that of the gate-to-source capacity. Therefore, thegate-to-drain or “Miller” capacitance typically requires more actual charge than the input capacitance.

To account for both gate-to-source and gate-to-drain capacitance in a way readily usable by designers, International Rectifiersupplies a “gatecharge” specificationsfor its IGBTs andHEXFET POWERMOSFETs. that canbe used to calculatedrive circuitrequirements. Gatecharge is defined asthe charge that mustbe supplied to thegate, either to swingthe gate by a givenamount, or to achievefull switching.

2. Test Circuit

A typical test circuitthat can be used to measure the gate charge is shown in Figure 1. In this circuit, an approximately constant current is supplied tothe gate of the device-under-test from the 0.1 microfarad capacitor C1, through the regulator diode D1. A constant current in thedrain circuit is set by setting the voltage on the gate of HEXFET POWER MOSFET 1, so the net measurement of the chargeconsumed by the gate is relative to a given current and voltage in the source-to-drain path.

5V5-10 MSEC

500Hz

100pF

1K51ΩΩ

3 1/2DS0026

U1A

1

22pF

4.7K

5

+V

4V-

U1B

+20V

.1µµF

8

7

1N414B

.1µµF

+20V

C1

1W5301

D1

+

-

100ΩΩ

IG VGS

DUT

+

-

9V 100K

.1µµF

ID SET

.68µµF

100ΩΩ2W

HEXFET 1

ID MONITOR

Figure 1. HEXFET POWER MOSFET Gate Charge Circuit.

AN-944 (v.Int)

An oscillogram of the gate-to-source voltage during testing,shown in Figure 2, relates the gate voltage to time. Since aconstant current is supplied to the gate, the horizontal timescale is directly proportional to the charge supplied to thegate. With a suitable scaling factor, therefore, this oscillogramis a plot of gate voltage versus charge. The point on theoscillogram of the second voltage rise indicates where thedevice is fully switched on. During the first voltage rise, thegate-to-source capacitance is charging, and during the flatportion, the gate-to-drain capacitance is charging. Thisoscillogram therefore clearly differentiates between the chargerequired for the gate-source and gate-to-drain (“Miller”)capacitances. At the second voltage rise, both capacitances arecharged to the extent needed to switch the given voltage andcurrent. A more detailed explanation of the interpretation ofthis data is given later. The graph in Figure 3 represents gatevoltage versus gate charge in nanocoulombs for an IRF130.Although the second voltage rise indicates the point at whichthe switching operation is completed, normal design safetymargins will dictate that the level of drive voltage applied tothe gate is greater than that which is just required to switchthe given drain current and voltage. The total chargeconsumed by the gate will therefore in practice be higher thanthe minimum required-but not necessarily significantly so.For example, the gate charge required to switch 12 amps at 80volts is 15 nanocoulombs (point A), and the correspondinggate voltage is about 7 volts.If the applied drive voltage has an amplitude of 10 volts (i.e.a 3 volt margin), then the total gate charge actually consumedwould be about 20 nanocoulombs, (point B). As shown on thegraph, whether switching 10 volts or 80 volts in the draincircuit, there is a much less than proportional difference in thecharge required. This is because the “Miller” capacitance is anonlinear function of voltage, and decreases with increasingvoltage.

The importance of the gate charge data to the designer is illustratedas follows. Taking the charge are required to switch a previousexample, about 15 nanocoulombs of gate if 1.5 amps is supplied to thegate, the device will be drain voltage of 80 volts and a drain currentof 12 amps. Since the 15 nC gate charge is the product of the gateinput current and the switching time, switched in 10 nS. It followsthat if 15 mA is supplied to the gate, then switching occurs in 1 ms,and so on. These simple calculations immediately tell the designer thetrade-offs between the amount of current available from the drivecircuit and the achievable switching time. With gate charge known,the designer can develop a drive circuit appropriate to the switchingtime required.Consider a typical practical example of a 100 kHz switcher, in whichit is required to achieve a switching time of 100 nanoseconds.

OPW 2 VZR 0 2V 2µµS

1 WFM 2 WFM WFM

OPW 0 VZR 0 2V 2µµS

0 WFM 0 WFM WFM

OPW 3 VZR 0 2V 2µµS

2 WFM 3 WFM WFM

0 5 10 15 20 25 30

2

4

6

8

10

12

14

ID = 1A

ID = 12AA

B

C

10V10V80V80V

VDS =

VG

S V

OLT

S

QG NANOCOULOMBS

Figure 2. Gate Charge Waveform for Different Values of DrainVoltage (IRF130: lG = 1.5 mA, ID =1A, VDD = 10, 40 and 80 volts).

Figure 3. Gate Voltage Versus Gate Charge for theIRF130.

AN-944 (v.Int)

Figure 4. Basic Gate Charge Test Circuit

The required gate drive current is derived by simply dividing the gate charge, 15 X 10-9, by the required switching time, 100 X10-9, giving 150 mA. From this calculation, the designer can further arrive at the drive circuit impedance. If the drive circuitapplies 14 volts to the gate, for instance, then a drive impedance of about 50 ohms would be required. Note that throughout the“flat” part of the switching period (Figure 3), the gate voltage is constant at about 7 volts. The difference between the applied 14volts and 7 volts is what is available to drive the required current through the drive circuit resistance.The gate charge data also lets the designer quickly determine average gate drive power. The average gate drive power, PDRIVE, isQGVGf. Taking the above 100 kHz switcher as an example, and assuming a gate drive voltage VG of 14 volts, the appropriatevalue of gate charge QG is 27 nanocoulombs (point C on Figure 3). The average drive power is therefore 27 X 10-9 X 14 X 105 =0.038 Watts. Even though the 150 mA drive current which flows during the switching interval may appear to be relatively high.the average power is minuscule (0.004%) in relation to the power being switched in the drain current. This is because the drivecurrent flows for such a short period that the average power is negligible. Thus actual drive power for MOSFETs is minutecompared to bipolar requirements, which must sustain switching current during the entire ON condition. Average drive power, ofcourse, increases at higher frequencies, but even at 5 MHz it would be only 1.9W.

3. The Gate Charge Curve

The oscillograms of the gate-to-source voltage in Figure 2 neatly delineate between the charge required for the gate-to-sourcecapacitance, and the charge required for the gate-to-drain, or “Miller” capacitance. The accompanying simplified test circuit andwaveform diagram ( Figures 4 and 5 respectively) give the explanation. Before time t0, the switch S is closed; the device undertest (DUT) supports the full circuit voltage, VDD, and the gate voltage and drain current are zero. S is opened at time t0; the gate-to-source capacitance starts to charge, and the gate-to-source voltage increases. No current flows in the drain until the gatereaches the threshold voltage. During period T1 to t2, the gate-to-source capacitance continues to charge, the gate voltagecontinues to rise and the drain current rises proportionally. So long as the actual drain current is still building up towards theavailable drain current, ID, the freewheeling rectifier stays in conduction, the voltage across it remains low, and the voltage acrossthe DUT continues to be virtually the full circuit voltage, VDD. The top end of the drain-to-gate capacitance CAD thereforeremains at a fixed potential, whilst the potential of the lower end moves with that of the gate. The charging current taken by CAD

during this period is small, and for practical purposes it can be neglected, since CAD is numerically small by comparison withGCS.At time t2, the drain current reaches ID, and the freewheeling rectifiershuts off; the potential of the drain now is no longer tied to the supplyvoltage, VDD. The drain current now stays constant at the value IDenforced by the circuit, whilst the drain voltage starts to fall. Since thegate voltage is inextricably related to the drain current by the intrinsictransfer characteristic of the DUT (so long as operation remains in the“active” region), the gate voltage now stays constant because the“enforced” drain current is constant. For the time being therefore, nofurther charge is consumed by the gate-to-source capacitance, becausethe gate voltage remains constant. Thus the drive current now diverts,in its entirety, into the “Miller” capacitance CAD, and the drive circuitcharge now contributes exclusively to discharging the “Miller”capacitance. The drain voltage excursion during the period t2 to t3 is relatively large,and hence the total drive charge is typically higher for the “Miller”capacitance CAD than for the gate-to-source capacitance GCS. At t3 thedrain voltage falls to a value equal to ID x RDS(ON) , and the DUT nowcomes out of the “active” region of operation. (In bipolar transistorterms, it has reached “saturation.” The gate voltage is now no longer constrained by the transfer characteristic of the device to relate to the drain current, and is freeto increase. This it does, until time t4, when the gate voltage becomes equal to the voltage “behind” the gate circuit currentsource. The time scale on the oscillogram of the gate-to-source voltage is directly proportional to the charge delivered by thedrive circuit, because charge is equal to the product of current and time, and the current remains constant throughout the wholesequence. Thus the length of the period t0 to t1 represents the charge QGS consumed by the gate-to-source capacitance, whilst thelength of the period t2 to t3 represents the charge QGD consumed by the gate-to-drain or "Miller" capacitance. The total charge attime t3 is the charge required to switch the given voltage VDD and current ID. The additional charge consumed after time t3 doesnot represent “switching” charge; it is simply the excess charge which will be delivered by the drive circuit because the amplitudeof the applied gate drive voltage normally will be higher (as a matter of good design practice) than the bare minimum required toaccomplish switching.

IGS

CGSS

G

CDG D

ID

+VDD

AN-944 (v.Int)

4. Beware When Comparing DifferentProducts

Manufacturers sometimes make technical claims fortheir products that appear to be plausible, but whichin actuality do not stand up to scrutiny. A case inpoint concerns the input capacitance of a powerMOSFET. Statements such as “the input capacitanceof device Y is less than that of device X, ergo Y is afaster switch than X”, are frequently bandied about,but are just as frequently erroneous. Apart from theobvious speciousness of many such statements —“apples” are frequently not compared with “apples”,and obviously larger chips have more self capacitancethan smaller ones—the more basic fundamentals aregenerally overlooked. As this application note shows,of “bottom line” importance is the total gate chargerequired for switching. The lower the charge, thelower is the gate drive current needed to achieve agiven switching time.A general comparison between hypotheticalMOSFETs brands “X” and “Y” is illustrated in theFigure. Device X has a higher input capacitance;hence the initial slope of its gate charge characteristicis less than that of device Y. QGS of device X is,however, about the same as that of device Y, becauseit has a higher transconductance and therefore requires lessvoltage on its gate for the given amount of drain current(VGX is less than VGY) The “Miller” charge consumed bydevice X is considerably less than that consumed by deviceY. The overall result is that the total charge required toswitch device X, QX, is considerably less than that requiredto switch device Y, QY. Had the comparison between devicesX and Y been made on the more superficial basis of inputcapacitances, it would have been concluded— erroneously—that Y is “better” than X. Another consideration is theenergy required for switching. Again, device X scoreshandsomely over device Y in this example. The energy is theproduct of the gate charge and the gate voltage, and isrepresented by the area of the rectangle whose corner lies atthe “switching point”. (Point 1 for device X, and point 2 fordevice Y.) It is obvious that X requires significantly less gateenergy than Y. To summarize: beware of superficialcomparisons. Check the full facts before deciding whichMOSFET really has the edge in switching performance.

Related Topics:

Gate drive considerations for IGBT modulesGate drive characteristics of IGBTsGate drive requirements of MOS-gated transistorsHigh-voltage gate drive ICsThree-phase gate drive ICGate drive IC for ballastsTransformer-isolated gate driver

VG(TH)

t0 t1 t2 t3 t4

QGS QGD

VG

GATEVOLTAGE

VDD

DRAINVOLTAGE

DRAIN CURRENT

ID

WAVEFORM

t

DEVICE X1

QY

QDGY

DEVICE Y 2

VG

QDGY

VGY

VGX

0

QX

QDGX

AREA OF THISRECTANGLE(0,2 DIAGONAL CORNERS)IS GATE ENERGYFOR DEVICE Y

Q

AREA OF THISRECTANGLE(0,1 DIAGONAL CORNERS)IS GATE ENERGYFOR DEVICE X

Figure 6. Comparison of Gate Charge Characteristics of DifferentDevice Types.

Figure 5. Basic Gate Charge Waveforms

AN-950 (v.Int)

Transformer-Isolated Gate Driver Provides very large duty cycle ratios(HEXFET® is the trademark for International Rectifier Power MOSFETs)

Transformer coupling of low level signals to power switches offers severaladvantages such as impedance matching. DC isolation and either step up orstep down capability. They also provide negative gate bias to reduce the riskof “dv/dt induced turn-on”.

Unfortunately, transformers can deliver only AC signals since the core fluxmust be reset each half cycle. This “constant volt seconds” property oftransformers results in large voltage swings if a narrow reset pulse, i.e., alarge duty cycle is required (Figure 1).

NOTE: VOLT-SECONDS PRODUCT IN SHADED AREAS MUST BEEQUAL. THIS CAUSES RESET VOLTAGE TO BE 3 TIMES APPLIEDVOLTAGE E.

Figure 2. Wide Duty Cycle HEXFET Power MOSFET Driver circuit

For this reason transformers in semiconductor drive circuits are limited to 50%, duty cycle or roughly equal pulse widths positiveand negative because of drive voltagelimitations of the semiconductorsthemsevles. For large duty cycleratios designers must choose analternative to the transformer, such asan optical coupler to provide thenecessary drive isolation.

Optoisolators for power electronicsrequire high dV/dt capability and areexpensive. They also requireadditional floating power sourceswhich add complexity and cost. Mostof them require a buffer stage tohandle the large gate capacitances,typical of power devices. If dutycycles are such that optoisolators arethe only alternative, they can be usedin a more cost-effective way asdrivers for a MOS-gate driver.

The circuit in Figure 2 provides a low impedance turn-on drive, and minimum pulse widths (on or off) of approximately 1microsecond; furthermore, it can have any desired voltage ratio, and provides electrical isolation. In Figure 2, Q2 is the mainpower device, shown as a MOSFET, providing the switching function for a switching power supply, motor drive or otherapplication requiring isolation between the low level logic and high power output. Ql is a low power HEXFET Power MOSFETsuch as the IRLML2803, which is used to control the drive signals to Q2, and T1 is a small 1:1 driver transformer providingelectrical isolation from, and coupling to, the low level circuitry.

T

T/3

E

-3E

Z1T1

1:1

Q1

Q2POWER SWITCH

+12V

0

-12V

+12V

0

-12V

+12V

0

-12V

0

A

B

C

D

LOW LEVEL LOGIC SIGNAL

T1 WINDING VOLTAGE

VGS POWER HEXFET Q2

VDS POWER HEXFET Q2

Figure 1. Constant-Volt-SecondsCharacteristics of Transformers

Figure 3. Waveform Characteristics of HEXFET POWER MOSFET Driver Circuit

AN-950 (v.Int)

Figure 4. Single Switch Regulators

The waveforms in Figure 3explain the circuit operation.Waveform A is the desired logicsignal to be switched by Q2.When this voltage is applied tothe primary of T1 the waveform issupported by changing core fluxuntil saturation occurs as shownin waveform B. At this time thewinding voltages fall to zero andremain so until the core flux isreversed by the negative-goingportion of waveform A saturationwill again occur if the negative-applied pulse exceeds the volt-seconds capability of the core.

During the positive portion of the secondarywaveform, which, of course, has the same formas the primary, the intrinsic diode of Ql is inforward conduction and Q2 receives a positivegate drive voltage with a source impedance ofZ1 plus the intrinsic diode forward impedance.

In a practical circuit this can be less than 10Ohms total, with a consequent turn-on time ofaround 75nsec.

When T1 saturates, the intrinsic diode of Q1isolates the collapse of voltage at the windingfrom the gate of the power device and the inputcapacitance Ciss of the power switch holds thegate bias at the fully enhanced condition for atime limited only by the gate leakage current ofQ2 as indicated in Figure 3c.

When waveform A goes 12 volts negative Qlwill become fully enhanced; and the mainswitch Q2 will now be turned off atapproximately -12V at a source impedance Z1 +RDS(ON) of Q2.

This will again be less than 10 Ohms and willyield a turn-off time less than 100nsec.

When T1 again saturates, during the negativehalf cycle, its winding voltages fall to zero andQ1 turns off. As T1 voltage collapses, the gateof Q2 also follows this voltage and remains atzero bias.

The drain voltage of the power HEXFETPower MOSFET Q2 appears in Figure 3d, showingthat it is indeed a mirror image of waveform A, the desired low level logic signal.

Note that because T1 need only support a 12V signal, for 1msec or less, it is very small—and inexpensive. In a practical circuitZ1 is frequently a 0.1 mF capacitor, and the signal source is a low impedance driver such as a PWM controller or gate driver.

GROUNDREFERENCE

LOGIC

VOVIN

IRFD1ZO

IRF840

IRFD1ZO

IRF840

IRFD1ZO

IRF840

IRFD1ZO

IRF840

HEXFETAVALANCEPROTECTION

Figure 5. High Voltage, High Power HEXFET Power MOSFET Switch(500V, 8A per Section)

AN-950 (v.Int)

It should be noted that the circuit in Figure 3(b) may not provide the necessary noise immunity when the power device is off. Thegate-source voltage of Q2 in the OFF state returns to zero when T1 saturates and the only noise immunity is provided by thethreshold voltage of Q2 (2V < VTH < 4V). In most applications it may be desirable to provide more noise immunity, by addinganother small N-Channel HEXFET Power MOSFET (typically another IRLML2803) as shown in Figure 7.

The circuit now provides -12V to the power MOSFET after the transformer saturates, and this reverse bias remains until thenext positive half cycle of drive. Thus, a minimum of 14V noise immunity is provided which should be adequate for all applica-tions. The cost and noise immunity of this solution is much less than alternatives using optoisolators and their auxiliary supplies.

Figures 5 and 6 show two applications where this gate drive method is particularly advantageous. The first is a high-voltage,high-frequency switch. The second is a bi-directional ac switch.

Transformer T 1 Considerations

In the circuits illustrated, the transformers were built from miniature tape wound or ferrite toroids. Typical part numbers forthese cores are as follows:

(1) Tape Wound CoresMagnetics Inc. #80558-(1/2D)MA

#52402-ID(2) Ferrite Toroids

Ferroxcube #266CT 125-3E2A or equivalent

Choice of a core type is not critical provided that 10 to 20 turns bifilar of suitable wire can be hand-wound onto it.

The size of core should be chosen so that adequate insulation thickness can be used for the isolation voltage requirements and toreduce interwinding capacitance.

Square Permalloy 80 cores are more expensive than ferrite types, but they have much narrower hysteresis loops and hence needfewer ampere turns of excitation. This can make a critical difference when the driver has limited current capability.

Bifilar windings improve the magnetic coupling of primary to secondary. and it is also important to space the turns to occupy360° of the core circumference to minimize leakage inductance. Unity turn ratios between primary and secondary also serve tominimize leakage inductance and hence optimize the transformer coupling coefficient.

Related Topics:

MOS-gate driversNegative gate bias

IRFD1Z0 IRFD1Z0

ON

OFF

IRFD1Z0IRF840

IRF840

INTRINSICDIODES

ADDITIONALCAPACITANCE FOR

LONG SWITCHPERIODS

Figure 7. Driver Circuit with additionalNoise Immunity

Figure 6. Bi-directional AC Switch using HEXFET POWERMOSFET

www.irf.com 19/14/99

IRF740ASMPS MOSFET

HEXFET® Power MOSFET

l Switch Mode Power Supply ( SMPS )l Uninterruptable Power Supplyl High speed power switching

Benefits

Applications

l Low Gate Charge Qg results in Simple Drive Requirementl Improved Gate, Avalanche and dynamic dv/dt Ruggednessl Fully Characterized Capacitance and Avalanche Voltage and Currentl Effective Coss specified ( See AN 1001)

VDSS Rds(on) max I D400V 0.55Ω 10A

Parameter Max. UnitsID @ TC = 25°C Continuous Drain Current, VGS @ 10V 10ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 6.3 AIDM Pulsed Drain Current 40PD @TC = 25°C Power Dissipation 125 W

Linear Derating Factor 1.0 W/°CVGS Gate-to-Source Voltage ± 30 Vdv/dt Peak Diode Recovery dv/dt 5.9 V/nsTJ Operating Junction and -55 to + 150TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )°C

Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)

Absolute Maximum Ratings

TO-220AB SDG

PD- 92004

Notes through are on page 8

Typical SMPS Topologies:

l Single transistor Flyback Xfmr. Resetl Single Transistor Forward Xfmr. Reset ( Both for US Line Input only )

IRF740A

2 www.irf.com

Parameter Min. Typ. Max. Units Conditionsgfs Forward Transconductance 4.9 ––– ––– S VDS = 50V, ID = 6.0AQg Total Gate Charge ––– ––– 36 ID = 10AQgs Gate-to-Source Charge ––– ––– 9.9 nC VDS = 320VQgd Gate-to-Drain ("Miller") Charge ––– ––– 16 VGS = 10V, See Fig. 6 and 13 td(on) Turn-On Delay Time ––– 10 ––– VDD = 200Vtr Rise Time ––– 35 ––– ID = 10Atd(off) Turn-Off Delay Time ––– 24 ––– RG = 10Ωtf Fall Time ––– 22 ––– RD = 19.5Ω,See Fig. 10 Ciss Input Capacitance ––– 1030 ––– VGS = 0VCoss Output Capacitance ––– 170 ––– VDS = 25VCrss Reverse Transfer Capacitance ––– 7.7 ––– pF ƒ = 1.0MHz, See Fig. 5Coss Output Capacitance ––– 1490 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHzCoss Output Capacitance ––– 52 ––– VGS = 0V, VDS = 320V, ƒ = 1.0MHzCoss eff. Effective Output Capacitance ––– 61 ––– VGS = 0V, VDS = 0V to 320V

Dynamic @ T J = 25°C (unless otherwise specified)

ns

Parameter Typ. Max. UnitsEAS Single Pulse Avalanche Energy ––– 630 mJIAR Avalanche Current ––– 10 AEAR Repetitive Avalanche Energy ––– 12.5 mJ

Avalanche Characteristics

S

D

G

Parameter Min. Typ. Max. Units ConditionsIS Continuous Source Current MOSFET symbol

(Body Diode)––– –––

showing theISM Pulsed Source Current integral reverse

(Body Diode) ––– –––

p-n junction diode.VSD Diode Forward Voltage ––– ––– 2.0 V TJ = 25°C, IS = 10A, VGS = 0V trr Reverse Recovery Time ––– 240 360 ns TJ = 25°C, IF = 10AQrr Reverse RecoveryCharge ––– 1.9 2.9 µC di/dt = 100A/µs ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Diode Characteristics

10

40

A

Parameter Typ. Max. UnitsRθJC Junction-to-Case ––– 1.0RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/WRθJA Junction-to-Ambient ––– 62

Thermal Resistance

Static @ T J = 25°C (unless otherwise specified)Parameter Min. Typ. Max. Units Conditions

V(BR)DSS Drain-to-Source Breakdown Voltage 400 ––– ––– V VGS = 0V, ID = 250µA∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.48 ––– V/°C Reference to 25°C, ID = 1mA

RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.55 Ω VGS = 10V, ID = 6.0A VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA

––– ––– 25µA

VDS = 400V, VGS = 0V––– ––– 250 VDS = 320V, VGS = 0V, TJ = 125°C

Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30VGate-to-Source Reverse Leakage ––– ––– -100

nAVGS = -30V

IGSS

IDSS Drain-to-Source Leakage Current

IRF740A

www.irf.com 3

Fig 4. Normalized On-ResistanceVs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

0.01

0.1

1

10

100

0.1 1 10 100

20µs PULSE WIDTHT = 25 CJ °

TOP

BOTTOM

VGS15V10V8.0V7.0V6.0V5.5V5.0V4.5V

V , Drain-to-Source Voltage (V)

I ,

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

DS

D 4.5V

0.1

1

10

100

0.1 1 10 100

20µs PULSE WIDTHT = 150 CJ °

TOP

BOTTOM

VGS15V10V8.0V7.0V6.0V5.5V5.0V4.5V

V , Drain-to-Source Voltage (V)

I ,

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

DS

D

4.5V

-60 -40 -20 0 20 40 60 80 100 120 140 1600.0

0.5

1.0

1.5

2.0

2.5

3.0

T , Junction Temperature ( C)

R

, D

rain

-to-

Sou

rce

On

Res

ista

nce

(Nor

mal

ized

)

J

DS

(on)

°

V =

I =

GS

D

10V

10A

0.1

1

10

100

4.0 5.0 6.0 7.0 8.0 9.0 10.0

V = 50V20µs PULSE WIDTH

DS

V , Gate-to-Source Voltage (V)

I ,

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

GS

D T = 25 CJ °

T = 150 CJ °

IRF740A

4 www.irf.com

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.Drain-to-Source Voltage

Fig 7. Typical Source-Drain DiodeForward Voltage

0 10 20 30 400

4

8

12

16

20

Q , Total Gate Charge (nC)

V

, G

ate-

to-S

ourc

e V

olta

ge (

V)

G

GS

FOR TEST CIRCUITSEE FIGURE

I =D

13

10A

V = 80VDS

V = 200VDS

V = 320VDS

0.1

1

10

100

0.2 0.4 0.6 0.8 1.0 1.2 1.4

V ,Source-to-Drain Voltage (V)

I

, Rev

erse

Dra

in C

urre

nt (

A)

SD

SD

V = 0 V GS

T = 25 CJ °

T = 150 CJ °

1

10

100

10 100 1000

OPERATION IN THIS AREA LIMITEDBY RDS(on)

Single Pulse T T

= 150 C= 25 C°

°JC

V , Drain-to-Source Voltage (V)

I ,

Dra

in C

urre

nt (

A)

I ,

Dra

in C

urre

nt (

A)

DS

D

10us

100us

1ms

10ms

1 10 100 1000

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

10000

100000

C, C

apac

itanc

e(pF

)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZCiss = Cgs + Cgd, Cds SHORTED

Crss = Cgd Coss = Cds + Cgd

IRF740A

www.irf.com 5

Fig 10a. Switching Time Test Circuit

VDS

90%

10%VGS

td(on) tr td(off) tf

Fig 10b. Switching Time Waveforms

VDS

Pulse Width ≤ 1 µsDuty Factor ≤ 0.1 %

RD

VGS

RG

D.U.T.

10V

+-VDD

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current Vs.Case Temperature

0.001

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01 0.1 1 10

Notes:1. Duty factor D = t / t2. Peak T = P x Z + T

1 2

J DM thJC C

P

t

t

DM

1

2

t , Rectangular Pulse Duration (sec)

The

rmal

Res

pons

e(Z

)

1

thJC

0.010.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE(THERMAL RESPONSE)

25 50 75 100 125 1500.0

2.0

4.0

6.0

8.0

10.0

T , Case Temperature ( C)

I ,

Dra

in C

urre

nt (

A)

°C

D

IRF740A

6 www.irf.com

QG

QGS QGD

VG

Charge

D.U.T.VDS

IDIG

3mA

VGS

.3µF

50KΩ

.2µF12V

Current RegulatorSame Type as D.U.T.

Current Sampling Resistors

+

-

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche EnergyVs. Drain CurrentFig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

tp

V (B R )D SS

I A S

R G

IA S

0 .0 1Ωtp

D .U .T

LV D S

+- VD D

D R IVER

A

1 5V

20V

25 50 75 100 125 1500

200

400

600

800

1000

1200

1400

Starting T , Junction Temperature ( C)

E

, S

ingl

e P

ulse

Ava

lanc

he E

nerg

y (m

J)

J

AS

°

IDTOP

BOTTOM

4.5A 6.3A 10A

Fig 12d. Typical Drain-to-Source VoltageVs. Avalanche Current

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

IAV , Avalanche Current ( A)

480

500

520

540

560

580

V D

Sav

, A

vala

nche

Vol

tage

( V

)

IRF740A

www.irf.com 7

P.W.Period

di/dt

Diode Recoverydv/dt

Ripple ≤ 5%

Body Diode Forward DropRe-AppliedVoltage

ReverseRecoveryCurrent

Body Diode ForwardCurrent

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P.W.Period

+

-

+

+

+-

-

-

Fig 14. For N-Channel HEXFETS

* VGS = 5V for Logic Level Devices

Peak Diode Recovery dv/dt Test Circuit

RG

VDD

• dv/dt controlled by RG• Driver same type as D.U.T.• ISD controlled by Duty Factor "D"• D.U.T. - Device Under Test

D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer

*

Transistores IGBTs, características, aplicações e circuitos de comando

René Pastor Torrico Bascopé e Arnaldo José PerinINEP – Instituto de Eletrônica de Potência

Departamento de Engenharia Elétrica – Centro Tecnológico – UFSCCaixa Postal 5119 – 88040-970 – Florianópolis - SC

1 - ESTRUTURA FÍSICA E PRINCÍPIO DE OPERAÇÃO DO IGBTDesde que se desenvolveu o primeiro no fim de 1957, tem surgido grandes progressos no desenvolvimento de

dispositivos semicondutores de potência. Até 1970, os tiristores convencionais foram utilizados de maneira exclusivapara o controle da energia elétrica em aplicações industriais. A partir de 1970, foram desenvolvidos os semicondutorestotalmente controlados de potência (na entrada em condução e no bloqueio) para sua aplicação no desenvolvimento deconversores estáticos de potência.

O IGBT tornou-se comercialmente disponível na década de 80 com a primeira geração. A evolução das gerações decada fabricante ocorre de uma maneira similar como é mostrado no exemplo da Fig. 1 [1]. Observando as curvas da Fig.1, é possível dizer que, com a evolução, os dispositivos tem possibilitado a diminuição das perdas de condução devidoàs cada vezes menores queda de tensão em estado de condução VCesat. Ao mesmo tempo, tem possibilitado umacomutação cada vez mais rápida, o que diminui as perdas de comutação.

0 0,1 0,2 0,3 0,4 0,50

0,5

1

3

1,5

2

2,5

3,5

VCEsat

0,6

t [ s]

0,7 0,8 0,9 1,0

µf

[V] 4

4,5

primeira geração

segunda geração

terceira geração

quarta geração

Fig. 1 - Curvas típicas de evolução das gerações dos IGBTs.1.1 – CARACTERÍSTICAS GERAIS

Para vencer as limitações dos transistores bipolares e MOSFET, realizou-se uma integração de suas vantagens:capacidade de corrente de coletor (característica do transistor bipolar) e controle por tensão aplicado entre gate-emissor(característica do MOSFET de potência), num único dispositivo híbrido que denomina-se transistor IGBT (InsulatedGate Bipolar Transistor). Este dispositivo pertence à família de dispositivos bi-MOS, sendo atualmente o maisavançado em tecnologia disponível e o mais utilizado comercialmente pelas características indicadas a seguir [2]:

•••• Controle por tensão: a entrada em condução e o bloqueio do dispositivo são controlados aplicando-se tensãoentre gate e emissor. A característica de entrada é idêntica ao MOSFET de potência: sua elevada impedância de entradadenota simplicidade para o circuito de comando, implicando em baixos custos.

•••• Baixas perdas de condução: o canal do IGBT, em estado de condução, é consideravelmente menos resistivo pelofato de ter-se o substrato P junto ao coletor, responsável pela injeção dos portadores minoritários (lacunas) na camadaresistiva do canal (N-base). O fluxo de corrente de coletor é dado pelos portadores minoritários.

•••• Elevada capacidade de corrente de coletor: pelo fato de apresentar uma característica de saída idêntica aotransistor bipolar de potência, o dispositivo possui uma elevada capacidade de condução de corrente de coletor(centenas de ampères).

•••• Operação em tensões elevadas: com o incremento da espessura das camadas do substrato N-base, foi possívelalcançar tensões de operação acima de 1000V [3], sem ocorrer o incremento da resistência do canal, fato este queacontece no MOSFET de potência.

•••• Não apresenta problemas de segunda avalanche: o dispositivo pode suportar simultaneamente elevadas tensõese correntes de curta duração sem apresentar problemas de destruição pelo fenômeno de segunda avalanche.

♦♦♦♦ Operação em Altas freqüências : é possível operar o interruptor até 200kHz em condições de comutação nãodissipativa [7].

Em condições de comutação dissipativa o IGBT pode operar até freqüências de 25kHz. Devido às perdas decomutação pela presença da corrente de cauda (que ocorre na transição do estado condução-bloqueio), a escolha dafreqüência de operação do transistor, dependerá das condições de comutação (Hard Commutation ou SoftCommutation).

Na literatura, este dispositivo também é conhecido como Conductivity Modulated Field-Effect Transistor(COMFET)[5].

Por natureza, os IGBTs são mais rápidos que os transistores bipolares de potência (BJT) por não apresentarem oproblema do tempo de estocagem, porém são menos rápidos que os transistores MOSFETs de potência.

COLETOR

P+

P-BASE P-BASE

N-BASE

N+N+N+ N+

EMISSOR GATE

METAL

EMISSOR

J1

J2

J3

TmodR

2

1

RT

st

SiO (Dióxido de Silício)2

Fig. 2 - Estrutura física e circuito equivalente do IGBT canal N.1.2 – ESTRUTURA FÍSICA

A estrutura física de um transistor IGBT canal N é mostrada na Fig. 2 e consiste basicamente de quatro camadas:substratos P+, N-base, P-base e N+. A sua construção é baseada no semicondutor de silício (Si). Para mudar suascaracterísticas elétricas e torná-lo um melhor condutor, é realizado o processo de dopagem, que consiste na adição, aosemicondutor, de elementos químicos em pequena proporção. A estrutura é constituída de camadas de substratos quesão chamados P e N. O substrato tipo P é obtido dopando o silício com elementos químicos trivalentes (três elétrons nacamada externa de valência), que podem ser: Boro, Gálio ou Índio. Por outro lado, o substrato tipo N é obtido dopandoo silício com elementos químicos pentavalentes (cinco elétrons na camada externa de valência), que podem ser: Fósforoou Antimônio [6].

No IGBT, a camada P+ é um substrato com forte dopagem de Boro (pouco resistiva) e a camada N-base é umsubstrato com dopagem de Fósforo (altamente resistiva). A formação da junção entre estas duas camadas permite ainjeção de portadores minoritários no canal quando o IGBT está no estado de condução, reduzindo-se desta maneira demodo considerável a queda de tensão e, por conseqüência, a potência dissipada internamente, neste estado [2]. Esteprocesso também é conhecido como modulação de condutividade. A modulação de condutividade no caso de umMOSFET não é favorável, pois o canal é constituído por elementos altamente resistivos (substrato tipo N) e a maiorparte das suas perdas ocorre nesta região em estado de condução, tipicamente 70% num dispositivo de 500V [8].

A presença das quatro camadas gera um tiristor parasita, composto pelos transistores bipolares PNP e NPN, comomostram a Fig. 2 e a Fig. 3. A operação deste tiristor é altamente indesejável, pois provoca a perda do controle dacorrente de coletor e, como conseqüência, a sua respectiva destruição por aquecimento. Para evitar sua destruição, aresistência Rst do substrato P-base (Fig. 1) deve ser bem baixa, de maneira a reduzir a queda de tensão à valoresinferiores a 0,6 V (o transistor parasita NPN não deve ser polarizado). O componente MOSFET canal N do circuitoequivalente, tem a função de controlar a corrente de base do transistor PNP durante sua operação. Na realidade, noIGBT a corrente de coletor é basicamente controlada através deste componente, dado pelos substratos N-base, P-base eN+.1.3 – PRINCÍPIO DE OPERAÇÃO

Como o IGBT resulta da combinação de uma estrutura MOS e de uma estrutura bipolar, sua análise difere de ambosos dispositivos de potência. Para compreender sua operação, é necessário o conhecimento da física do transistorMOSFET e do transistor bipolar. Nesta seção é descrito o princípio de operação do dispositivo e, para tal finalidade,não é considerada a situação da operação do tiristor parasita que provoca perda de controle da corrente de coletor.

Gate

Coletor

Emissor

NPN

PNPT

T

R

iCTiristor

Rmod 1

2

st

ibasePNPMOSi

(Coletor)

(Gate)

(Emissor)

E

G

C

Fig. 3 - Circuito equivalente do IGBT Canal N e o seu símbolo.1.3.1 – Capacidade de bloqueio reverso

O IGBT não entra em condução (fluxo de corrente de coletor) quando uma tensão negativa entre coletor-emissor (-VCE) é aplicada, apesar de ter-se uma tensão positiva entre gate-emissor (VGE) acima do valor de limiar (thresholdvoltage), pelo simples fato da junção J3 (formada entre as camadas P+ e N-base) estar polarizada reversamente. Apolarização reversa da junção provoca a formação de uma camada de depleção na região, garantindo desta maneira acapacidade de bloqueio reverso do dispositivo. Esta característica é mostrada através da Fig. 3. É importante deixarclaro que a tensão de ruptura reversa, depende essencialmente da espessura da camada resistiva N-base. As duastecnologias modernas existentes atualmente, PT (Punch-Through) e NPT (Non-Punch-Through), relativas à estrutura do

dispositivo, apresentam características de saída diferentes [9].

VCE

I

VCER

C

ICR

característica diretacaracterística reversa

região ativa

incremento datensão de gate

Fig. 4 - Característica de saída do IGBT (genérico)1.3.2 – Capacidade de condução direta

Para que o IGBT encontre-se em estado de condução direta (forward conduction), é necessário aplicarsimultaneamente tensões positivas entre gate-emissor (VGE) e coletor-emissor (VCE). Aplicando-se estas duas tensões,vence-se a depleção da junção J2 entre as camadas P-base N-base e a depleção da junção J3 entre as camadas P+ N-base(ambas as junções devem ser polarizadas diretamente). A tensão gate-emissor positiva deve ser suficientementeelevada, acima da tensão de limiar, para que a resistência do canal MOS seja pequena durante o fluxo de corrente decoletor. A resistência no canal do IGBT é baixa devido à modulação de condutividade, proporcionada pela injeção deportadores minoritários (lacunas) desde a região P+ dentro da região N-base altamente resistiva. A densidade deportadores minoritários injetados na região N-base é tipicamente de 100 a 1.000 vezes maior que o nível de portadoresda camada N-base do MOSFET de potência. Por este motivo é reduzida drasticamente a resistência do canal do IGBTem relação à resistência do canal do MOSFET de potência. Esta característica permite operar o IGBT com elevadasdensidades de corrente durante o estado de condução. Como a camada N-base do IGBT deixa de ser altamente resistivacom a injeção de portadores minoritários, para aumentar a capacidade de operação com tensões acima de 1.000V ésuficiente aumentar a espessura desta camada.1.3.3 – Capacidade de bloqueio direto

O bloqueio do IGBT, quando encontra-se em estado de condução, é alcançado reduzindo-se a tensão entre gate eemissor abaixo do valor de limiar (VGEth – Gate-Emitter Threshold Voltage). A tensão abaixo do valor de limiar éalcançada curto-circuitando o terminal gate ao terminal emissor com um resistor de baixo valor de resistência. Com estacondição, a junção J2 é polarizada reversamente bloqueando o fluxo de corrente através do canal MOS do dispositivo. Obloqueio é realizado em condições de tensão coletor-emissor positiva. Observando o circuito equivalente do IGBTmostrado na Fig. 3, o bloqueio da corrente de coletor do IGBT é realizado através do MOSFET que bloqueia a correntede base do transistor PNP.

t

t

VGE

iC

t1

∆ I ccauda

t

iC

aumento de R GE

vCE

aumento de R GE

iC

vCE

Fig. 5 - Características de bloqueio e corrente de coletor com a variação de RGE durante o bloqueioA característica de saída do IGBT é controlada através da tensão aplicada entre gate-emissor VGE. Para realizar a

transição do estado de condução ao estado de bloqueio, o gate, que inicialmente tem um valor positivo de tensão, éligado ao emissor por um circuito externo, provocando-se a descarga da capacitância intrínseca de entrada dada peloparalelo das capacitâncias entre coletor-gate e gate-emissor. A descida abrupta da tensão entre gate e emissor até umvalor abaixo do limiar permite, como conseqüência, um decrescimento abrupto da corrente de coletor até um certovalor. Como resultado, tem-se a súbita redução à zero da corrente do canal MOS devido aos elétrons. A magnitude daqueda abrupta da corrente de coletor - ∆IC - no instante t

1 (Fig. 5), é grande devido ao baixo ganho de corrente (βPNP),do transistor PNP do circuito equivalente, que situa-se na faixa de 0,4 a 0,5. Isto implica que a corrente de base dotransistor PNP, que é a mesma corrente que flui pelo canal MOS é igual a: ibasePNP = iMOS = iC/(1+βPNP). Após cairabruptamente, a corrente de coletor decresce continuamente de maneira mais lenta devido à alta densidade deportadores minoritários injetados na região N-base. Tais portadores necessitam de tempo para sua recombinação, o queresulta numa corrente de coletor residual indesejada que somente causa perda de energia durante a comutação debloqueio do dispositivo. Esta corrente residual é conhecida na literatura como corrente de cauda (tail current) [7].

A queda abrupta da corrente de coletor (∆Ic) causa variações de corrente de coletor (dic/dt) de elevado valor, quedevido à presença de indutâncias parasitas do layout e do próprio dispositivo, geram elevadas tensões sobre ointerruptor durante o bloqueio, muitas vezes podendo provocar sua destruição. Esta queda abrupta pode ser alteradacontrolando-se a tensão entre gate-emissor durante o bloqueio. Isto é alcançado com a descarga lenta da capacitância deentrada através de uma resistência adequada ligada entre gate e emissor durante o bloqueio. Na Fig. 5 é mostrada a

diminuição da corrente de coletor (dic/dt) com o incremento do valor do resistor conectado entre gate e emissor duranteo bloqueio. É importante indicar que com o incremento do valor do resistor conectado entre gate e emissor (RGE)durante o bloqueio, o efeito da redução da corrente de cauda, corrente indesejada, é ínfima [5] ( Fig. 5).

2 - CIRCUITOS DE COMANDOPelo fato de apresentar uma impedância de entrada elevada, o IGBT é controlado por um sinal de tensão adequado

aplicado entre gate e emissor VGE, requerendo baixa potência da fonte de tensão do circuito de comando de gate. Umavantagem do IGBT em relação ao MOSFET, para uma mesma capacidade de corrente nominal, é a baixa capacitânciade entrada determinando um baixo consumo de energia [10].

O circuito de comando de gate deve permitir uma operação adequada do interruptor IGBT nos estados de condução,comutação na entrada em condução e no bloqueio, proporcionando também o isolamento entre o circuito de controle e ocircuito de potência, evitando sua possível destruição devido aos diferentes potenciais de tensão de coletor e emissor.Com um circuito bem projetado as perdas de condução e comutação são mínimas com moderados esforços de tensão ecorrente, protegendo o dispositivo da destruição.2.1 – PERDAS E ESFORÇOS RELACIONADOS AO COMANDO

2.1.1 - Comutação na Entrada em ConduçãoPara analisar as perdas e esforços e relacioná-las ao circuito de comando, é considerado o circuito de potência em

meia ponte (half-bridge) com carga indutiva mostrado na Fig. 6. Este circuito apresenta dois interruptores no braçooperando complementarmente com comutação dissipativa. Neste tipo de configuração os dispositivos suportam osmaiores esforços de sobretensão e sobrecorrente, cujos fenômenos serão explicados a seguir.

Aplicando um pulso positivo de tensão entre os terminais gate-emissor VGE de valor acima do limiar (∼5V), o IGBTentra em condução. Para minimizar a perda de comutação na entrada em condução (turn-on) o tempo de subida (risetime) da corrente de coletor (iC) deve ser o menor possível. Para alcançar esta característica, o tempo de subida datensão entre os terminais gate-emissor VGE deve ser também o menor possível, já que este tempo reflete-se no tempo desubida da corrente de coletor. Isto pode ser conseguido carregando-se rapidamente a capacitância de entrada Cies dodispositivo (que constitui-se das capacitâncias gate-emissor CGE e gate-coletor CGC, ou capacitância Miller) por meio deuma fonte de tensão de baixa impedância durante a aplicação do pulso. Uma elevada tensão de gate ajuda a transferirrapidamente a carga necessária, vencendo os efeitos das resistências e indutâncias parasitas do circuito de comando degate.

E2

E1L

L

D1

D2

IGBT1

IGBT2 Carga Indutiva

braço

RG(on)

RG(off)

RG(off)

RG(on)

VG1

VG2

0

0tm = tempo mortotm

s1

s2

Fig. 6 - Circuito em meia ponte para a análise dos tempos de comutação.Por outro lado, diminuindo-se o tempo de subida da corrente de coletor, provoca-se um crescimento abrupto da

mesma, aumentando a magnitude da corrente de recuperação reversa do diodo em antiparalelo com o IGBTcomplementar. Além disso, provoca elevadas interferências de rádio freqüência (RFI) e eletromagnéticas (EMI), bemcomo sobretensão no interruptor complementar devido à presença de indutâncias parasitas (Ls1 e Ls2) que existem nocircuito de potência e que podem ser diminuídas através de um layout apropriado (v=Ls.dic/dt).

Aconselha-se portanto, a colocação de uma resistência RG(on) de baixo valor em série com o gate do dispositivo,como é mostrado na Fig. 5. Deste modo, é possível controlar o tempo de subida da corrente de coletor do IGBT, ou seja,o valor de diC/dt.

Observa-se que deve existir um compromisso de otimização de perdas e esforços de sobretensão, pois ambasgrandezas se relacionam. No caso de persistir a sobretensão, pode-se limitá-la em um valor dentro da área RBSOA, coma utilização de um circuito externo (circuito snubber, circuito grampeador, etc.). A resistência de gate, portanto,apresenta importância fundamental no rendimento e custo do conversor.

Para o caso de cargas resistivas, quando o sinal de tensão gate-emissor sobe rapidamente na entrada em condução, atensão coletor-emissor VCE desce rapidamente. Esta descida rápida provoca uma dvCE/dt que injeta correntes dentro docircuito de comando através da capacitância coletor-gate CCG. Estas derivadas de tensão podem causar oscilações detensão de gate, permitindo o aumento de perdas na entrada em condução. A pequena resistência RG(on) indicadaanteriormente em série com o gate do dispositivo, também permite reduzir estas derivadas de tensão, embora asindutâncias parasitas do circuito de comando possam ser minimizadas colocando-se o circuito de comando o maispróximo possível do dispositivo.

Quando a comutação finaliza, a tensão sobre o dispositivo, tensão coletor-emissor, encontra-se num valor muitobaixo (tensão de saturação) e este valor depende da tensão gate-emissor VGE.2.1.2 - Em Estado de Condução

O valor da tensão de saturação coletor-emissor VCEsat deve ser o menor possível, desta maneira minimiza-se asperdas em estado de condução, sendo portanto conveniente aplicar uma tensão gate-emissor elevada (na faixa de 12V a

15V). Na prática, muitos dos fabricantes de IGBTs recomendam aplicar-se uma tensão de 15V e uma resistência RG(on)

em série com o gate menor que 50Ω [11]. O valor da resistência em série com o gate normalmente é dimensionadoconforme as correntes máximas que podem suportar os dispositivos do circuito de comando (transistores de sinal, portaslógicas, etc.) e analisando os efeitos de diC/dt e dvCE/dt.

Quando a tensão de saturação é bem baixa devida à aplicação de uma tensão elevada entre gate-emissor VGE, amagnitude da corrente de cauda é maior. Portanto, existe uma dependência entre estes dois parâmetros.2.1.3 - Comutação no Bloqueio

Durante a comutação de bloqueio os IGBTs, apesar do tempo de retardo, não apresentam tempos de estocagemcomo normalmente acontece com os transistores bipolares.

O tempo de descida da corrente de coletor do IGBT compõem-se basicamente do tempo de descida da corrente debase do transistor bipolar pnp (circuito equivalente da Fig. 3, corrente que flui pelo canal MOS), controlada por meio dogate e do tempo de descida da corrente de cauda (devido à parcela de corrente de coletor do mesmo transistor). Acorrente de cauda é provocada pela recombinação de portadores minoritários no transistor pnp do circuito equivalente,não podendo ser reduzida por meios externos (através do circuito de comando). As perdas de comutação de bloqueio emum IGBT com comutação dissipativa, não mudam significativamente através do circuito de comando de gate variando aresistência RG(off), já que a maior perda de potência é devida à parcela de corrente de cauda.

No IGBT não é necessário um sinal de tensão negativo entre os terminais gate-emissor VGE; sua aplicação dependerádo tipo de topologia e dos efeitos que provoca (diC/dt, dvCE/dt) sobre os dispositivos. Uma resistência de bloqueioRG(off), de baixo valor, entre gate-emissor é suficiente para proporcionar um caminho de descarga da capacitância gate-emissor, permitindo o bloqueio do IGBT. Para operar o IGBT em alta freqüência (acima de 10kHz) num braço (half-bridge), a presença de um pulso negativo de tensão gate-emissor VGE é importante durante o bloqueio para reduzir osefeitos de dvCE/dt que injetam correntes através do capacitor gate-coletor CGC no capacitor gate-emissor CGE,provocando picos de tensão gate-emissor acima do valor de limiar. Este picos de tensão podem provocar uma conduçãoindevida do dispositivo complementar.

Com relação ao tempo de subida (rise time) da tensão coletor-emissor VCE durante o bloqueio, quanto menor for estetempo, maiores serão os valores de dvCE/dt entre os terminais coletor-emissor do dispositivo. Uma das maneiras dereduzir os efeitos devido às elevadas derivadas de tensão, é dimensionando adequadamente a resistência RG(off) em sériecom o gate. Um outro problema que pode provocar um elevado dvCE/dt no bloqueio é o fenômeno de latch-up - entradaem condução do tiristor parasita devido ao fluxo de corrente capacitivo interno [10].

A presença da resistência de bloqueio de gate RG(off) durante a comutação de bloqueio, tem uma influência diretasobre o tempo de retardo do bloqueio do IGBT; este fenômeno é ilustrado na Fig. 7.a e Fig. 7.b para dois valores deresistências diferentes. Como pode-se observar, quanto maior for o valor desta resistência, maior será o tempo deretardo.

0

V = -15VGE(off)

G(off) Ω

IC

VGE

V CE

R = 0

Fig. 7.a - Formas de onda de: tensão coletor-emissor, tensão gate-emissor e corrente de coletor. Módulo IRGTA090F06, testadoem: 380V, 100A; Ls = 100nH. VCE: 100V/div, IC: 50A/div, VGE: 10V/div, tempo: 200ns/div [10].

0

V = -15VGE(off)

G(off) Ω

IC

VGE

V CE

R = 33

Fig. 7.b - Formas de onda de: tensão coletor-emissor, tensão gate-emissor e corrente de coletor. Módulo IRGTA090F06, testadoem: 380V, 100A; Ls = 100nH. VCE: 100V/div, IC: 50A/div, VGE: 10V/div, tempo: 200ns/div [10].

A tensão negativa de gate durante o bloqueio reduz o tempo de retardo de bloqueio, pois permite uma rápidadescarga da capacitância de entrada do IGBT.2.1.4 - Em Estado Bloqueado

Como já foi dito anteriormente, durante a comutação de bloqueio e estado bloqueado, é suficiente manter conectadoo terminal de gate ao terminal de emissor através de uma resistência de bloqueio RG(off) de baixo valor. Porém, no casodos interruptores estarem em um braço de um conversor e atuando de modo complementar, é importante aplicar uma

tensão negativa durante todo o intervalo de tempo que se quer manter o IGBT bloqueado, para evitar que sinais espúriosde tensão positiva provoquem a entrada em condução indevida. No caso de um conversor em meia ponte (Fig. 6) ossinais espúrios de tensão gate-emissor podem provocar um curto-circuito de braço, destruindo os IGBTs.

Para obter características de operação favoráveis, é possível aplicar-se uma tensão negativa na faixa de 5V a 15V.Segundo [10] é recomendado aplicar-se uma tensão negativa de 5V e uma resistência RG(off) série de gate de bloqueiomenor que 47Ω. O valor do pulso negativo pode ser maior que 5V, sem restrições quanto aos níveis da tensão epotência do conversor. Em algumas aplicações, normalmente costuma-se utilizar uma resistência única para ambos osestados de operação do dispositivo. Também existem critérios de utilização de resistências com valores diferentes,sendo uma para cada estado de operação, ou combinação em paralelo de ambas utilizando diodos de sinal em série.Toda escolha depende do critério do projetista do circuito de comando. Convém lembrar que durante a operação dodispositivo, podem acontecer transitórios destrutivos de tensão entre os terminais gate-emissor. Para proteger odispositivo de tais condições indesejáveis, devem ser utilizados diodos zener diretamente conectados entre os terminaisgate-emissor, tanto para o pulso positivo como para o pulso negativo.2.2 – NECESSIDADE DE CIRCUITOS DE COMANDO ISOLADOS

Em circuitos de potência em ponte, os IGBTs inferiores têm os emissores conectados a um ponto comumconsiderado normalmente como nó de referência, onde o potencial de tensão relativo é nulo, portanto, para estesinterruptores pode não ser necessário utilizar circuitos de comando de gate isolados. Quando não é utilizado isolamentoexiste o perigo de destruição do circuito de controle devido ao potencial de tensão de coletor do IGBT por destruição dealgum dispositivo do circuito de comando conectado ao coletor do IGBT (caso de circuitos com proteção de curto-circuito por detecção de dessaturação). Por este motivo, em conversores com circuitos de controle complexos e comcircuitos de proteção, recomenda-se utilizar circuitos de comando de gate isolados para todos os interruptores depotência.

Os IGBTs superiores, porém, têm seus emissores conectados a diferentes potenciais de tensão em relação aopotencial de referência, o que torna necessário utilizar circuitos de comando de gate isolados. Para realizar o isolamentopodem ser utilizados transformadores de pulso, optoacopladores e circuitos de comando de gate integrados dedicados. Oprojeto do circuito de comando de gate isolado deve levar em consideração o custo, imunidade a ruídos, complexidade,rapidez de resposta, etc..2.2.1 - Transformadores de Pulso

O transformador de pulso é um dispositivo magnético do circuito de comando de gate que opera em elevadafreqüência e que proporciona isolamento galvânico entre os circuitos de potência e circuito de controle, com o empregode um enrolamento primário e um ou mais enrolamentos secundários. Este dispositivo pode transmitir pulsos de tensãodo primário para o secundário sem distorção e com atrasos quase desprezíveis. Quando é aplicado um transformador depulso em um circuito de comando, não se faz necessário utilizar uma fonte de tensão isolada no lado do secundário,podendo, ainda, operar favoravelmente em freqüências de comutação elevadas (acima de 100kHz). Outra vantagem desua aplicação, é a imunidade à interferências por ruído, não apresentando também, problemas por elevados valores dedvCE/dt.

Para que o transformador apresente um desempenho adequado no circuito de comando, devem ser levados emconsideração os seguintes tópicos:

• Tensão de isolamento do transformador (> 4kV);• Mínima indutância de dispersão;• Freqüência de operação;• Dimensionamento adequado do núcleo e número de espiras do primário e secundário;• Capacidade de transferência de energia para dispensar o uso de fonte auxiliar no lado secundário;• Limitação da variação da razão cíclica prevenindo a saturação do núcleo (desmagnetização do núcleo).

Normalmente quando é aplicado o método comum de transmissão de pulsos, ao primário não devem ser aplicadospulsos com razão cíclica acima de 50% por motivo de saturação do núcleo. Neste método, a razão cíclica dos pulsospodem variar desde valores próximos a zero até 0,5.

Para conseguir a transmissão de pulsos com razão cíclica acima de 50%, técnicas convenientes de desmagnetizaçãodo núcleo devem ser utilizadas, onde a razão cíclica dos pulsos pode variar de ∼0 a ∼100%.2.2.2 - Optoacopladores

Os optoacopladores são dispositivos do circuito de comando de gate que proporcionam isolamento elétrico entre oscircuitos de controle e potência. Possuem a vantagem de transmitir pulsos com freqüência variável e com qualquerrazão cíclica, sem apresentar problemas de saturação como no caso do transformador de pulso. Porém, apresentamdesvantagens quando comparados a estes: necessitam uma fonte auxiliar isolada na sua saída, circuitos para amplificar acorrente de saída (que é da ordem de 20mA), apresentam pouca imunidade a interferências por ruídos, bem comoproblemas devido à elevados dvCE/dt (estes problemas estão sendo superados com as últimas gerações deoptoacopladores). Em relação à freqüência de operação, os mesmos limitam-se a, no máximo, 100 kHz.

Alguns detalhes devem ser observados para otimizar o uso de optoacopladores:• Devem apresentar imunidade à ruídos e derivadas de tensão;• Os sensores de sinal devem ser fotodiodos (os fototransistores são lentos);• As capacitâncias entre a entrada e a saída devem ser pequenas;

• Aplicar aproximadamente a corrente nominal na entrada para a polarização do fotodiodo;• Optar por dispositivos com elevada tensão de isolamento entre a entrada e a saída (> 4kV);• Levar em consideração possíveis recomendações adicionais do fabricante indicadas no catálogo, como por

exemplo: capacitores de desacoplamento, distância das trilhas de circuito impresso, etc.2.2.3 - Circuitos de Comando Integrados Dedicados

Atualmente muitos fabricantes de IGBTs tem desenvolvido circuitos de comando de gate integrados dedicados paraseus dispositivos. Existem circuitos com isolamento e sem isolamento. Alguns destes circuitos necessitam de uma fontede tensão isolada na saída. Os circuitos com isolamento utilizam fotosensores de sinal ou transformadores de pulso paratransmitir os pulsos da entrada para a saída (circuitos de comando da Mitsubishi, Fuji, Semikron, etc.) e, os circuitossem isolamento utilizam a técnica do Bootstrap (circuitos da International Rectifier) que normalmente são utilizados emconversores de baixa potência (< 2kW ) e baixa tensão (< 600V). Alguns circuitos ainda podem apresentar proteçãocontra curto-circuito. Mais adiante serão mostrados alguns deles.2.3 – EXEMPLOS DE CIRCUITOS DE COMANDO ISOLADOS

O circuito de potência (chopper) mostrado na Fig. 8 foi utilizado para testar os circuitos de comando para um únicotransistor. O tiristor neste circuito é utilizado para simular um curto-circuito na carga. Por outro lado, o circuito depotência em meia ponte da Fig. 9, foi utilizado para testar os circuitos de comando integrados para um braço deinterruptores.

E2

C

100V

R3

G

E

D1R1

IRGPH40F D2R2

C1

C2

C3

SCR

Tiristor para simularcurto-circuito

Fig. 8 - Circuito a IGBT para teste dos circuitos de comando de gate.

O IGBT do conversor da Fig. 8 apresenta as seguintes especificações:VCE = 1200V,VCEsat = 3V @ IC = 17A, TJ = 150oC.VGE = +/- 20V,ICN = 17A @ TC = 100oC, ICM = 58A,

C2

C1

R1=10

C1

G1

E1

C2

G2

E2

R2

C3

D1

100V

MÓDULO : CM15TF - 12E

Ω

Fig. 9 - Circuito em meia ponte para teste dos circuitos de comando de gate.Por outro lado, o módulo IGBT em meia ponte do conversor da Fig. 9 apresenta as seguintes especificações:VCE = 600V,VCEsat = 2,7V @ IC = 15A, TJ = 150oC,VGE = +/- 20V,ICN = 15A @ TJ = 25oC, ICM = 30A @ TJ = 25oC,Um circuito de comando de gate (isolado ou não) é considerado adequado para acionar um IGBT, quando têm as

seguintes características: mantêm aproximadamente igual a razão cíclica do pulso da tensão de entrada ao circuito Vconno pulso da tensão positiva na saída do circuito VGE; o pulso da tensão de saída não sofre distorção em relação ao pulsoda tensão de entrada; é capaz de aplicar níveis adequados de tensão gate-emissor e corrente de gate. Os pulsos de tensãopodem apresentar atrasos na subida e na descida como é mostrado na Fig. 10, porém, as magnitudes de tais atrasosdevem ser aproximadamente iguais td(on) ≅ td(off) , para manter quase inalterado o valor da razão cíclica.2.3.1 – Circuitos de comando isolados por transformador de pulso

Estes circuitos são capazes de aplicar pulsos de tensão gate-emissor positivos de 15V e negativos de 5V. Doiscircuitos não realizam proteção de curto-circuito do IGBT mas outros dois circuitos realizam proteção de curto-circuitodo IGBT por detecção de dessaturação através da tensão coletor-emissor VCE.

t d(on) t d(off)

t

t

vcon

vGE

50%

50%50%

50%

50%

0

0

Fig. 10 - Pulsos de tensão de entrada e de saída de um circuito de comando.♦ CIRCUITO A1 :

Vcc1

Z5

R6

R5Q2 R7

D1

Z2

Tr

R2

Q1

R3

C1 R4Z3 C2 Z4

E

R1Z1

vcon

vcon

t

15VV

IGpk

GE

D2

D3

G

Fig. 11 - Circuito de comando de gate isolado com transformador de pulso e sem proteção de curto-circuito para 0 <<<< D ≤≤≤≤ 0,5.A seguir é dada uma metodologia para determinar algumas grandezas importantes para o dimensionamento do

circuito de comando, tais como: corrente de pico de gate para entrada em condução do IGBT, energia necessária paragarantir a polarização do IGBT, etc. [11].

A corrente de pico (Igpk) fornecida pelo circuito de comando para carregar a capacitância de entrada (Cies) do IGBTdurante a entrada em condução, que é limitada pela resistência de gate, pode ser calculada de maneira aproximadautilizando-se a seguinte equação:

G

)off(GE)on(GEGpk R

VVI

−≅ (1)

Onde:VGE(on) : tensão positiva gate-emissor;VGE(off) : tensão negativa gate-emissor;RG : resistência de gate.No circuito de comando da Fig. 11, a resistência R6 é a resistência de gate (RG).Tomando os seguintes valores de tensões de gate-emissor e a resistência de gate:VGE(on) = 15VVGE(off) = -5VRG = R6 = 27Ω

e substituindo na Eq. 1, tem-se o valor da corrente de pico.

A74,027

)5(15IGpk =−−≅

A energia absorvida pelo IGBT do circuito de comando para a entrada em condução, pode ser determinada atravésda seguinte equação:

VQE )on(IGBT ∆⋅∆= (2)

Onde:∆Q : Variação de carga da capacitância de entrada [Cies];∆V : Variação da tensão gate-emissor [V].Estas grandezas podem ser obtidas a partir da característica de carga de gate mostrada no catálogo do dispositivo

(IGBT). Para ter maiores detalhes ver a literatura [12].No circuito da Fig. 8 utilizou-se o IGBT da International Rectifier ( IRGPH40F ) como dispositivo de teste. Da

característica de carga de gate mostrada no catálogo foram obtidos os seguintes dados.∆Q ≅ [50 - (-10)] = 60 ηC∆V ≅ [15-(-5)] = 20 VÉ importante esclarecer que na figura de característica de carga de gate deste dispositivo, não é mostrada a curva de

carga para a tensão negativa gate-emissor, que é necessária para o cálculo da energia. Para solucionar esta situação foirealizada uma interpolação aproximada e determinada a carga para tensão negativa.

Substituindo os valores obtidos da curva na Eq. 2, a energia é igual a:EIGBT(on) = 1,2 µJA potência da fonte de tensão do circuito de comando absorvida pelo IGBT durante a entrada em condução, que é

dissipada no resistor de gate (R6), pode ser determinada com a seguinte equação:S)on(IGBT)on(IGBT fEP ⋅= (3)

Onde:fS : Freqüência de comutação do IGBTPara as freqüências de comutação de 10kHz e 50kHz as potências são iguais a 12mW e 60mW.A energia necessária para bloquear o IGBT (energia para descarregar a capacitância de entrada) é igual à energia

necessária para a entrada em condução (energia para carregar a capacitância de entrada). Portanto, EIGBT(on) = EIGBT(off).Em um período de comutação, a potência fornecida ao IGBT pela fonte de tensão (VCC1) do circuito de comando, é

dissipada no resistor de gate sem considerar as perdas devido aos outros componentes do circuito de comando, édeterminada pela seguinte equação:

S)on(IGBT1Vcc fE2P ⋅⋅= (4)

As perdas provocadas pelos outros componentes do circuito de comando, podem ser determinadas comsimplicidade. Por exemplo, nos resistores são conhecidos os valores das resistências e as tensões sobre eles e nos diodoszener as correntes de polarização e suas tensões de operação indicadas no catálogo.

A seguir são explicados alguns detalhes para dimensionar os componentes do circuito da Fig. 8.• Capacitor C1: é um capacitor cerâmico que permite uma rápida entrada em condução e bloqueio do transistor Q1,

que opera na região de saturação. O valor de sua capacitância pode ser escolhida entre 3,3nF para uma freqüência decomutação de 10kHz a 680pF para uma freqüência de comutação de 50kHz. Este capacitor não deve provocar umadistorção do sinal de comando gerado pelo circuito de controle; portanto, conforme este critério deve ser escolhido oseu valor.

• Capacitor C2: é um capacitor eletrolítico que armazena energia durante a transmissão do pulso de tensão atravésdo transformador de pulso. A tensão sobre ele é grampeada no valor da tensão de operação do zener Z3. Sua energiadeve ser suficiente para garantir a descarga da capacitância de entrada do IGBT. Este capacitor comporta-se como umafonte de tensão negativa durante todo o bloqueio do dispositivo (IGBT). O valor de sua capacitância pode serdeterminada utilizando-se a seguinte equação:

23Z

)on(IGBT2

V

E2C

⋅> (5)

Para evitar sua descarga pela presença de outros dispositivos no circuito de comando e garantir o bloqueio do IGBT,deve ser escolhido um capacitor com capacitância maior que 10µF / 25V.

• Diodo D1: é um diodo de sinal utilizado simplesmente para polarizar o transistor de sinal Q2. A operação dotransistor é como segue: quando o diodo conduz, o transistor é bloqueado e quando o diodo é bloqueado, o transistorconduz.

• Diodos D2 e D3: são diodos de sinal colocados em série com as resistências R5 e R7 para evitar perdas e descargada energia do capacitor C2 durante o estado bloqueado do IGBT.

• Resistor R1: é utilizado para limitar a corrente de curto-circuito da fonte de tensão VCC1 no caso de eventualdestruição do transistor Q1. O valor não deve ser elevado, pois, pode provocar limitação do pulso de corrente de gatedurante a entrada em condução do IGBT. Na prática recomenda-se escolher de 10Ω a 27Ω.

• Resistor R2 : é utilizado para desmagnetizar a indutância de dispersão do transformador de pulso e amorteceroscilações. O valor pode ser escolhido de 1kΩ a 2kΩ.

• Resistor R3: limita a corrente de base do transistor de sinal Q1. Ele deve ser dimensionado para permitir aoperação do transistor na região de saturação. O valor de sua resistência pode ser determinada com o conhecimento dacorrente do secundário do transformador após o IGBT ter entrado em condução e que circula através do paralelo dasresistências de R6 + R7 com R4, que é aproximadamente a mesma corrente que circula através do coletor do transistorQ1, quando a relação de transformação do transformador de pulso é unitária. O excesso de corrente de base nestetransistor faz com que ele fique muito saturado aumentando o tempo de estocagem, tornando lento o seu bloqueio. Naprática pode-se utilizar a eq. 7.6 para o dimensionamento aproximado de R3.

Gpk

con3 I03,0

VR

⋅≅ (6)

• Resistor R4 : limita a corrente de base do transistor de sinal Q2. O valor pode ser escolhido entre 1kΩ a 2kΩ.• Resistor R5: o valor de sua resistência pode ser determinada com o conhecimento da corrente de polarização do

zener Z3 e a energia no capacitor C2 .• Resistor R6: é o resistor de gate (RG) que é utilizado para controlar dic/dt e dvCE/dt sobre o IGBT. Por outro lado,

limita a corrente através dos dispositivos do circuito de comando de gate. O valor de sua resistência deve ser escolhidoanalisando os esforços de tensão e da corrente do IGBT. Para o circuito da Fig. 8 foi escolhido uma resistência de gatede 27Ω para o estado de condução, que é a mesma utilizada para o estado de bloqueio [RG(on) = RG(off)].

• Resistor R7: permite a descarga da capacitância gate-emissor CGE do IGBT, quando na ausência do sinal decomando e/ou destruição do transistor Q2 é aplicada abruptamente uma tensão entre coletor-emissor VCE. O súbitocrescimento da tensão provoca uma derivada que induz uma corrente na capacitância gate-emissor CGE através dacapacitância coletor-gate e, como conseqüência, a tensão gate-emissor pode superar o valor de limiar permitindo aentrada em condução do IGBT. Por este motivo, sua aplicação é recomendada principalmente quando o circuito decomando for utilizado em um braço, para evitar problemas de curto-circuito. O valor desta resistência pode serescolhida de 470Ω a 2kΩ. Os diodos zener conectados entre gate e emissor, somente protegem o gate para tensões gate-

emissor acima de seu valor de operação.• Transistores Q1 e Q2: devem ser dimensionados com o prévio conhecimento da corrente de pico de coletor e

máxima tensão coletor-emissor.• Transformador de pulso Tr: o transformador pode ser projetado utilizando-se as equações dadas a seguir [13]:

3D

Ii maxGpkef ⋅≅ [A] (7)

swp

4efmax1cc

we fBJKK10iDV

AA⋅∆⋅⋅⋅

⋅⋅⋅≅⋅ [cm4] (8)

se

41ccmax

p fBA10VD

N⋅∆⋅⋅⋅

≅ [espiras] (9)

JiS ef

f ≅ [cm2] (10)

Onde:Ae : Área da seção transversal do núcleo [cm2];Aw : Área da janela do núcleo [cm2];∆B : Excursão do fluxo magnético [T];Dmax : Razão cíclica máxima;fs : Freqüência de comutação [Hz];ief : Corrente eficaz no primário do transformador [A];J : Densidade de corrente [A/cm2];Kp : Fator de utilização do primário;Kw : Fator de utilização da janela;NP : Número de espiras do primário;Sf : Seção do fio [cm2].Nota: estas equações são válidas para um núcleo de ferrite do tipo EE.• Zener Z1 e Z2: são utilizados para desmagnetizar o transformador de pulso. O zener Z1 limita a tensão coletor-

emissor reversa do transistor Q1 em seu valor de operação (quando a relação de transformação é unitária). Este zenerpode ser dimensionado com uma tensão de operação de 1,5 vezes a tensão no secundário do transformador de pulso.Quanto maior a tensão de operação de Z1, maior poderá ser a razão cíclica do pulso de tensão. Por outro lado, o zener Z2pode ser dimensionado com valor de tensão igual à tensão do secundário do transformador de pulso. O zener Z2,também pode ser substituído por um diodo de sinal rápido.

• Zener Z4 e Z5: são utilizados para evitar a destruição do IGBT pela presença de sobretensões entre gate e emissor,para pulsos de tensão positivos e negativos. Os valores de tensão de operação devem ser menores que a tensão dedestruição gate-emissor indicados pelos fabricantes ( ±20V).

Os transformadores dos circuitos de comando foram dimensionados para operar em uma freqüência de comutação(fs) de 10kHz. Para operar o circuito em freqüências na ordem de 25kHz, foi reduzido o valor da capacitância docapacitor C1. Embora não se tenha efetuado, deve-se também reduzir o número de espiras do primário e do secundáriodo transformador de pulso e o núcleo do transformador de pulso.

Para a aquisição das formas de onda mostradas na Fig. 12 foi utilizado o circuito de potência da Fig. 8, cujointerruptor IGBT foi acionado com o circuito de comando de gate da Fig. 11. Todas as aquisições foram efetuadas parauma freqüência de operação do interruptor igual a 25kHz.

Nas Figs. 12 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando (Vcon)e da tensão de saída gate-emissor (VGE) para as razões cíclicas 0,5 e 0,1. Em relação ao sinal de entrada (Vcon), na Fig.12 (a) o sinal de saída (VGE) apresenta um atraso na subida de 100ns e um atraso na descida de 200ns. Por outro lado, naFig. 12 (b) o sinal de saída (VGE) tem um atraso na subida de 100ns e um atraso na descida de 400ns. Os atrasos nadescida são maiores em relação à subida e aumentam com a diminuição da razão cíclica, por causa da demora (tempo deestocagem) no bloqueio do transistor bipolar Q1 do circuito de comando (Fig. 11). Este problema pode ser superadoutilizando-se um transistor MOSFET de sinal.

Na Fig. 12 (c) são mostradas as formas de onda dos pulsos da tensão gate-emissor VGE e da corrente de gate IG,durante a carga e a descarga da capacitância de entrada do IGBT.

Na Fig. 12 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor IC. Os testesdo circuito de comando foram realizados com estes níveis de tensão e de corrente.

As formas de onda das Figs. 12 (e) e (f), mostram os detalhes da comutação do interruptor do conversor da Fig. 11.Como pode-se perceber, o IGBT entra em condução sob condições de corrente nula devido às características indutivasda carga e bloqueia sob condições de tensão e corrente não nulas. Observando a última figura, a derivada da corrente decoletor provoca uma sobretensão sobre o IGBT devido à presença de indutâncias parasitas no circuito de potência. Poreste motivo, é recomendado desenvolver o circuito de potência com um ótimo layout.♦ CIRCUITO A2 :

O circuito da Fig. 13 possui uma proteção de sobrecorrente, devido à sobrecarga ou curto-circuito, baseada na

observação da tensão entre coletor e emissor. Sabe-se que, para uma determinada tensão de gate, se ocorrer um aumentoda corrente de coletor, aumenta também a tensão VCE. Deste modo, observando-se VCE pode-se detectar a existência desobrecorrente, devido a sobrecargas ou curtos-circuitos. A seguir são descritos os componentes que foram introduzidospara a proteção de sobrecorrente.

V

VGE

con

VGE

conV

(a) Vcon e VGE [5V/div.; 5µµµµs/div.] (b) Vcon e VGE [5V/div.; 5µµµµs/div.]

IG

VGE

IC

VCE

(c) VGE [10V/div.; 5µµµµs/div.] (d) VCE [20V/div.;10µµµµs/div.]iG [200mA/div.; 5µµµµs/div.] IC [2A/div.;10µµµµs/div.]

IC

VCE

VCE

IC

(e) VCE [20V/div.; 500ns/div.] (f) VCE [20V/div.; 500ns/div.]IC [2A/div.; 500ns/div.] IC [2A/div.; 500ns/div.]

Fig. 12 - Formas de onda obtidas com os circuitos das Figs. 8 e 12.Vcc1

R5 D2 R6 D3

G

C

Z5

R8

R7

Q3

D1

Z2

Q2

C3

Tr

R1

Q1

R3

C1 R4 Z3 C2 Z4E

R9R2

Z1

Z6

VGE

vcon

vcon

t

15VD5

D4

Fig. 13 - Circuito de comando de gate isolado com transformador de pulso e com proteção de curto-circuito para 0 <<<< D ≤≤≤≤ 0,5.• Capacitor C3 : permite a polarização do transistor bipolar Q2 para que o sinal de comando transmitido pelo

transformador de pulso chegue ao gate do IGBT. O IGBT, que inicialmente encontra-se com tensão coletor-emissor VCEigual ou maior que o valor da fonte de tensão do circuito de potência, deve alcançar a tensão coletor-emissor desaturação VCEsat antes que a tensão sobre o capacitor C3 alcance o valor de VGE(on) . O valor de C3 é determinadoconsiderando a corrente de coletor do transistor Q2 igual à corrente de pico de gate IGpk e de valor constante durante acomutação. Para este nível de corrente, observando a curva de característica de saída de transistor Q2 (catálogo) édeterminada a corrente de base IBQ2, que também é aproximadamente constante. Portanto, com estas considerações, ocapacitor C3 carrega-se com corrente aproximadamente constante. O circuito equivalente é mostrado na Fig. 14.

R6

C3IBQ2 C3v

Fig. 14 - Circuito equivalente durante a carga do capacitor C3 que ocorre na entrada em condução do IGBT.

A tensão inicial sobre o capacitor C3, antes da entrada em condução do IGBT, é aproximadamente igual a:3D6Z3C VV)0(v +≅ (11)

onde:VZ6 = 6,8 V : Tensão de operação do zener Z6;

VD3 = 0,7 V : Queda de tensão sobre o diodo D3 durante a condução.A variação linear de tensão sobre o capacitor é dada pela seguinte equação:

t)I3C

1()0(v)t(v 2BQ3C3C ⋅⋅+= (12)

Considerando a tensão final sobre o capacitor C3 de 0,8VGE(on) para um tempo de duração do pulso de corrente degate (tcom) de 400ns e substituindo na Eq. 12, obtém-se o valor da capacitância C3. Com esta consideração, a tensãocoletor-emissor (VCE) deve cair do valor máximo ao valor de saturação VCEsat antes que C3 possa carregarcompletamente. Quando a tensão coletor-emissor não atinge o valor de saturação durante este tempo previsto, o sinal decomando é inibido e como conseqüência o IGBT é bloqueado novamente. No caso da ocorrência desta situação o valorda capacitância deve ser aumentado experimentalmente.

Utilizando a Eq. 13, obtida a partir de Eq. 12, pode ser determinado o valor de C3:

)0(v]V8,0[tI

C3C)on(GE

com2BQ3 −⋅

⋅≅ (13)

Das curvas de característica de saída do transistor Q2 (2N2907) para a corrente de coletor ICQ2 = Igpk, a corrente debase IBQ2 é aproximadamente igual a 20 mA.

Substituindo valores na Eq. 13, o valor da capacitância é igual a:≅3C 1,8 ηF

Quando ocorre o curto-circuito de carga em estado de condução do IGBT, a tensão coletor emissor VCE cresce e odiodo D3 é bloqueado. A tensão sobre o capacitor C3 começa a crescer desde o valor inicial VC3(0) devido à corrente debase do transistor Q2. Quando a tensão sobre ele atinge o valor do potencial da base do transistor Q2, este transistor ébloqueado inibindo o sinal de comando de gate. A corrente de base que carrega o capacitor C3 depende da corrente decoletor. Portanto, para diminuir o tempo de bloqueio, o resistor R9 entre gate-emissor é ajustado para um baixo valor. Acorrente de base é determinada a partir das curvas de característica de saída do transistor Q2 (catálogo) como umafunção da corrente de coletor no instante do curto-circuito.

O tempo que demora para atuar a proteção pode ser estimado com a seguinte equação:[ ]

)curto(2BQ

3C)on(GE3blo I

)0(vVCt

−⋅= (14)

A corrente de coletor (ICQ2) durante o curto-circuito é igual à corrente que flui pelos resistores R4, R7 e R9, (IGpk ≅ 0),e seu valor é igual a ICQ2 = 35 mA. Uma vez conhecida a corrente de coletor, das curvas de característica de saída dotransistor Q2 (2N2907) a corrente de base é aproximadamente igual a : IBQ2(curto) = 2,5 mA. Logo, substituindo os valoresna Eq. 14, o tempo de bloqueio, após ocorrido o curto-circuito, é aproximadamente igual a:

tblo ≅ 5,4 µsOu seja, o IGBT poderá suportar correntes superiores a 6 vezes a corrente nominal até atuar a proteção, pois este

tempo será inferior a 10µs.• Diodo D3 : detecta a dessaturação da tensão coletor-emissor do IGBT. Este diodo deve ser ultra-rápido e com

tensão reversa de operação maior que a máxima tensão coletor-emissor do IGBT. Sua corrente média é muito pequena,menor que 100mA.

• Zener Z6: Permite detectar o curto-circuito com baixos valores da tensão coletor-emissor (VCE). Também evita adescarga do capacitor C3.

Para obter as aquisições das formas de onda mostradas na Fig. 15 foi utilizado o circuito de potência da Fig. 8, cujointerruptor IGBT foi acionado com o circuito de comando de gate da Fig. 13. Todas as aquisições foram obtidas parauma freqüência de operação do interruptor de 25kHz.

Nas Figs. 15 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon eda tensão de saída, gate-emissor VGE, para as razões cíclicas 0,5 e 0,1. Em relação ao sinal de entrada Vcon, na Fig. 15(a) o sinal de saída (VGE) apresenta um atraso na subida de 125ns e um atraso na descida de 225ns. Por outro lado, naFig. 15 (b), o sinal de saída VGE tem um atraso na subida de 125ns e um atraso na descida de 430ns. Do mesmo modoque no caso anterior, os atrasos na descida são maiores em relação à subida e aumentam com a diminuição da razãocíclica e isto ocorre por causa da demora do bloqueio do transistor bipolar Q1.

Na Fig. 15 (c) são mostradas as formas de onda da tensão gate-emissor (VGE) e da corrente de coletor durante o testede curto-circuito do IGBT. Observa-se na figura que o circuito de comando garante a proteção em aproximadamente5µs após detectada a falha. O tempo de duração do curto-circuito está abaixo do valor permitido, que é de 10µs. Poroutro lado, na Fig. 15 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletordurante o teste de curto-circuito do IGBT. Ressalta-se que ocorre uma sobretensão no bloqueio do IGBT devido àelevada derivada de corrente sobre indutâncias parasitas da malha formada por C2, D1 e IGBT1 da Fig. 8.♦ CIRCUITO A3 :

Os circuitos das Figs. 16 e 18 permitem operar os interruptores de potência com razão cíclica e freqüência variáveis,dentro de uma faixa de variação não muito elevada. Estes circuitos normalmente são aplicados em conversores commodulação PWM senoidal [14].

V

VGE

con

V

VGE

con

(a) Vcon e VGE [5Vdiv.;5µµµµs/div.] b) Vcon e VGE [5Vdiv.; 5µµµµs/div.]

VGE

IC

VCE

IC

(c) VGE [10V/div.; 10µµµµs/div.]; (d) VCE [50V/div.; 10µµµµs/div.]IC [50A/div.; 10µµµµs/div.] IC [50A/div.; 10µµµµs/div.]

Fig. 15 - Formas de onda obtidas com os circuitos das Figs. 8 e 12.• Capacitores C2 e C3: permitem uma corrente média nula nos enrolamentos primário e secundário para evitar a

saturação do transformador de pulso. Os valores das capacitâncias podem ser obtidos realizando a medição daindutância magnetizante do transformador e considerando a freqüência de ressonância (fr ) igual a 1/10 da freqüência decomutação (fs). A seguir são dadas as equações para determinar os valores de suas capacitâncias:

2

sm2 f2

10L1C

⋅π⋅

⋅≥ (15)

2

2

2

13 C

NN

C ⋅

= (16)

onde:Lm : Indutância magnetizante do primário do transformador;fs : Freqüência de comutação do IGBT;N1 : Número de espiras do primário do transformador;N2 : Número de espiras do secundário do transformador.•••• Capacitor C5 : permite um rápido bloqueio do transistor de sinal Q2 evitando o atraso na subida do sinal de

comando. Seu valor deve ser maior ou igual a 5,6nF.Vcc1

C3

D1Tr

Q3

vconQ4

Q5

R1 R2

Q1

C5Q2

C2

R3

C1

GZ3

R6

R5

D2

R4Z1

R7

C4Z2 E

VGE

vcon

t

15V

D3D4

Fig. 16 - Circuito de comando de gate isolado com transformador de pulso e sem proteção de Curto-circuito para 0 <<<< D <<<< 1.• Transformador de Pulso Tr : deve ser projetado de maneira similar ao do circuito da Fig. 11.• Dispositivos R1, R2, C5, Q1 e Q2 : são utilizados para polarizar os transistores de sinal Q3 e Q4. Se o nível de

tensão dos pulsos do circuito de controle (vcon) for maior ou igual ao valor de VCC1, estes dispositivos não sãonecessários.

Para a aquisição das formas de onda mostradas na Fig. 17 foi utilizado o circuito de potência da Fig. 8, onde ointerruptor IGBT foi acionado com o circuito de comando de gate da Fig. 16.

GEV

conV

GEV

conV

(a)Vcon e VGE [5V/div.;5µµµµs/div.] (b)Vcon e VGE [5V/div.;5µµµµs/div.]Fig. 17 - Formas de onda obtidas com os circuitos das Figs. 8 e 16.

Nas Figs. 17 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon e

da tensão de saída gate-emissor VGE para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada Vcon, na Fig. 17 (a)o sinal de saída VGE apresenta um atraso na subida de 350ns e um atraso na descida de 170ns. Por outro lado, na Fig. 17(b) o sinal de saída VGE tem um atraso na subida de 80ns e um atraso na descida de 150ns. O sinal de saída gate-emissortem um atraso na subida maior, em comparação com o atraso na descida, por causa do bloqueio lento do transistorbipolar Q2 do circuito da Fig. 17. O capacitor C5 que cumpre a função de permitir um bloqueio rápido deste transistortem menor energia quando aumenta a razão cíclica. Portanto, o atraso na subida diminui quando diminui a razão cíclica,devido a uma maior saturação do transistor Q4. Esta conclusão é confirmada com os resultados dos valores dos atrasospara a razão cíclica 0,1. Estes atrasos podem ser alterados modificando as correntes de base de Q3 e Q4 ou adicionando-se circuitos de anti-saturação.♦CIRCUITO A4

O circuito da Fig. 18 possui característica de proteção de sobrecorrente, além das características do circuitoanteriormente apresentado na Fig. 16.

Para a aquisição das formas de onda mostradas na Fig. 19 foi utilizado o circuito de potência da Fig. 8, onde ointerruptor IGBT foi acionado com o circuito de comando de gate da Fig. 18. Todas as aquisições foram efetuadas parauma freqüência de operação do interruptor de 25kHz.

Vcc1

C3

C2R2

Q4

Q5

R1

C5

Q1

Q2

Q3

TrR3

C1

R5 D3 R7 D4

G

C

Z2

R8

R6C6 R9

D2

D1

Q6

R4 Z1

Z4

C4

Z3

Evcon

VGE

vcon

t

15VD5

D6

Fig. 18 - Circuito de comando de gate isolado com transformadorde pulso e com proteção de curto-circuito para 0 <<<< D <<<< 1.

Nas Figs. 19 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon eda tensão de saída gate-emissor VGE para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada, na Fig. 19 (a), osinal de saída VGE apresenta um atraso na subida de 380ns e um atraso na descida de 180ns. Por outro lado, na Fig. 19(b), o sinal de saída VGE tem um atraso na subida de 80ns e um atraso na descida de 170ns. Neste circuito, as diferençasdos tempos de atrasos ocorrem pelos mesmos motivos indicados no circuito da Fig. 16.

GEV

conV

GEV

conV

(a)Vcon e VGE [5V/div.;5µµµµs/div.] (b)Vcon e VGE[5V/div.; 5µµµµs/div.]

VGE

IC

VCE

IC

(c) VGE [10V/div.; 10µµµµs/div.] (d) VCE [50V/div.; 10µµµµs/div.]IC [50A/div.; 10µµµµs/div.] IC [50A/div.; 10µµµµs/div.]

Fig. 19 - Formas de onda obtidas com os circuitos das Figs. 8 e 18.Na Fig. 19 (c) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor IC durante o

teste de curto-circuito do IGBT. Observa-se que o circuito de comando de gate garante a proteção do IGBT emaproximadamente 5,5µs após detectada a falha. O tempo de duração do curto-circuito é menor que o valor permitido,que é normalmente de 10µs no máximo.

Na Fig. 19 (d) são mostradas as formas de onda da tensão coletor-emissor (VCE) e da corrente de coletor durante aocorrência do curto-circuito do IGBT. Verifica-se que a rápida descida da corrente de curto-circuito provoca umasobretensão entre o coletor e o emissor do IGBT. Esta sobretensão em alguns casos pode provocar a destruição dodispositivo. Esta derivada de corrente de coletor pode ser diminuída aumentando o valor da resistência de gate. No casode não ser aumentado o valor da resistência de gate, a sobretensão pode ser limitada colocando-se um grampeador detensão entre coletor e emissor, projetado segundo a área de operação segura de bloqueio (RBSOA). A sobretensão éoriginada pelas indutâncias parasitas na malha formada por C2, D1 e IGBT1 da Fig. 8.2.3.1 – Circuitos de comando isolados por optoacoplador

Nas Figs. 20 e 22 são apresentados os circuitos de comando isolados por optoacoplador para acionar interruptoresIGBTs. Estes circuitos permitem aplicar pulsos de tensão gate-emissor positivos de 15V e negativos de 7,5V. Adiferença entre os dois circuitos é proteção de curto-circuito por detecção de saturação da tensão coletor-emissor do

IGBT realizada pelo circuito da Fig. 22. Todos os dispositivos destes circuitos são dimensionados de acordo com aslimitações de tensão e corrente do optoacoplador da Hewlett Packard (HCPL 2200) e exigências de corrente de gatepara entrada em condução e bloqueio do IGBT.♦CIRCUITO B1:

Para a aquisição das formas de onda mostradas na Fig. 21 foi utilizado o circuito de potência da Fig. 8, onde ointerruptor IGBT foi acionado com o circuito de comando de gate da Fig. 20. Todas as aquisições foram feitas para umafreqüência de operação do interruptor de 25kHz.

Vcc1

R3

C4

Q4 Z3

R6R7

GQ3

R8Q1

R5

Q2R4

8

R1

1

2

3

4 5

6

7Z2

C3

E

Z1

C5

C2

CI1 VGEvcon

t

15V

D1

HCPL2200

R2

C1

Fig. 20 - Circuito de comando de gate isolado com optoacoplador e sem proteção de curto-circuito.GEV

conV

GEV

conV

(a) Vcon e VGE[5V/div.;5µµµµs/div.] (b) Vcon e VGE[5V/div.;5µµµµs/div.]Fig. 21 - Formas de onda obtidas com os circuitos das Figs. 8 e 20.

Nas Figs. 21 (a) e (b) são mostradas a formas de ondas dos sinais da tensão de entrada do circuito de comando Vcon eda tensão de saída gate-emissor VGE para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada, na Fig. 21 (a), osinal de saída VGE apresenta um atraso na subida de 450ns e um atraso na descida de 400ns Por outro lado, na Fig. 21(b) o sinal de saída VGE tem um atraso na subida de 425ns e um atraso na descida de 400ns. Neste circuito os tempos deatraso na subida e na descida e em toda a faixa de variação da razão cíclica são aproximadamente iguais.

Observa-se que, com este circuito, é possível obter-se uma ampla faixa de variação de freqüências dos pulsos decomando que só é limitada nas altas freqüências por estes atrasos acima citados. Estes atrasos ainda poderiam serdiminuídos melhorando-se os tempos de bloqueio dos transistores Q2 a Q4.♦CIRCUITO B2:

Vcc1

R5

Q4

Q3R6R7

Q5

Z4

R8

D2 D3C

Z3

R9

G

D1 C6Q1Q2

R4

C5

C3

Z2E

C2

VGE

R10

D4

R3

C4

8

R1

1

2

3

4 5

6

7

Z1

CI1vcon

t

15V

HCPL2200

R2

C1

Fig. 22 - Circuito de comando de gate isolado com optoacoplador e com proteção de curto-circuito.Para a aquisição das formas de onda mostradas na Fig. 23 foi utilizado o circuito de potência da Fig. 8, onde o

interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 22. Todas as aquisições foram feitas para umafreqüência de operação do interruptor de 25kHz.

Nas Figs. 23 (a) e (b) são mostradas as formas de onda dos sinais de tensão de entrada do circuito de comando Vcon eda tensão de saída gate-emissor VGE para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada, na Fig. 23 (a), osinal de saída VGE apresenta um atraso na subida de 500ns e um atraso na descida de 450ns, por outro lado, na Fig. 23(b) o sinal de saída VGE tem um atraso na subida de 450ns e um atraso na descida de 425ns. Neste circuito as diferençasdos tempos de atraso na subida e na descida do sinal da tensão de saída, para toda a faixa de variação de razão cíclica,são aproximadamente iguais.

Na Fig. 23 (c) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor durante o testede curto-circuito do IGBT. Observa-se que o circuito de comando de gate garante a proteção do IGBT emaproximadamente 5,5µs após detectada a falha.

Na Fig. 23 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor durante aocorrência de curto-circuito do IGBT. Nesta aquisição é mostrado o detalhe do efeito da descida da corrente de curto-circuito que provoca uma sobretensão entre coletor e emissor devido às indutâncias parasitas do circuito de potência,sendo que em muitos casos, esta sobretensão pode ser destrutiva para o dispositivo.

conV

GEV

VGEVcon

(a) Vcon e VGE[5V/div.;5µµµµs/div.] (b) Vcon e VGE[5V/div.;5µµµµs/div.]

VGE

IC

VCE

I C

(c) VGE [10V/div.; 10µµµµs/div.] (d) VCE [50V/div.; 10µµµµs/div.]IC [50A/div.; 10µµµµs/div.] IC [50A/div.; 10µµµµs/div.]

Fig. 23 - Formas de onda obtidas com os circuitos das Figs. 8 e 22.2.3.3 – Circuitos de comando integrados

Nas Figs. 24 e 26 são mostrados os circuitos de comando integrados com isolamento para acionar interruptoresIGBTs. Estes circuitos permitem aplicar pulsos de tensão gate-emissor positivos de 15V e negativos de 7,5V. Nocircuito da Fig. 24 empregou-se somente dois dos três circuitos de comando isolados disponíveis no circuito integrado.Os sinais de comando utilizados possuem pulsos complementares com tempo morto ajustado através do circuito geradorde sinais e empregados nos interruptores do circuito da Fig. 26.♦CIRCUITO C1 :

O circuito integrado (CI1) da Fig. 24 é um circuito da Powerex/Mitsubishi que contém internamente três circuitos decomando isolados por optoacopladores, independentes, capazes de acionar três IGBTs com diferentes níveis depotencial de emissor.

É importante mencionar que os circuitos não realizam proteção alguma de curto-circuito do IGBT.Na aplicação do integrado no acionamento de IGBTs com diferentes potenciais de emissor, cada circuito de

comando deve possuir uma fonte de tensão isolada na saída. Agora, no caso de ter-se IGBTs com seus emissoresconectados a um nó comum, é necessário somente uma fonte de tensão na saída para todos os circuitos de comando queacionam estes dispositivos.

Para transmitir os pulsos de tensão da entrada para a saída, os circuitos requerem uma fonte de tensão na entradacom valor não maior que 5V (VCC1) como mostra a figura. Uma outra característica do circuito é a seguinte: para limitaras correntes de polarização de entrada, drenadas da fonte de 5V, não são necessários resistores externos, pois possueminternamente seus resistores.

6

Vcc1

C1

Q11

2

8

5

7

1216

R1

C1

Q1

11

18

15

17

26

CI1

R1

22

21 28

25

27

C1

Q1

R1

R2C2

Vcc2

R3

Z3

Z2

R4

G1

E1C3Z1

R2C2

Vcc2

R3

z3

Z2

R4

G2

E2C3Z1

R2C2

Vcc2

R3

Z3

Z4

R4

G3

E3C3Z1

vcon2VGE2

vcon1

15V

vcon1

vcon2

t

15V

VGE1t

M57919L

Fig. 24 - Três circuitos de comando de gate isolados independentes sem proteção de curto-circuito.Para a aquisição das formas de onda mostradas na Fig. 25 foram utilizados os circuitos de potência da Fig. 9, onde

os interruptores IGBTs foram acionados com os circuitos de comando de gate da Fig. 24. Todas as aquisições foramfeitas para uma freqüência de operação do interruptor de 25kHz.

Nas Figs. 25 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon eda tensão de saída gate-emissor VGE para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada, na Fig. 25 (a), o

sinal de saída VGE apresenta um atraso na subida de 650ns e um atraso na descida de 550ns. Por outro lado, na Fig. 25(b) o sinal de saída VGE tem um atraso na subida de 600ns e um atraso na descida de 550ns. Neste circuito as diferençasdos tempos de atrasos na subida e na descida são pequenos (esta afirmação é válida para freqüências menores que 40kHz) e estão dentro das especificações dadas no catálogo do componente (M57919L).

VGE

Vcon

conV

GEV

(a) Vcon e VGE[5V/div.;5µµµµs/div.] (b) Vcon e VGE[5V/div.;5µµµµs/div.]Fig. 25- Formas de onda obtidas com os circuitos das Figs. 9 e 24.

♦CIRCUITO C2O circuito da Fig. 26 foi desenvolvido para acionar dois IGBTs em uma configuração meia ponte. Neste circuito, os

circuitos de comando estão dados pelos circuitos integrados CI1 e CI3 da Powerex/Mitsubishi, ambos isolados poroptoacoplador.

No circuito de comando da figura o circuito integrado CI1 aciona o interruptor superior e o circuito integrado CI3aciona o interruptor inferior.

Estes circuitos integrados não realizam ajuste do tempo morto dos sinais de comando - que previne curto-circuito debraço. Portanto, o tempo morto deve ser ajustado no circuito de controle. Na ocorrência de curto-circuito em qualquerinterruptor do braço, os circuitos integrados CI1 e CI3 detectam a dessaturação da tensão coletor-emissor VCE por meiodo diodo conectado ao coletor D1 e inibem o sinal de comando de gate em aproximadamente 6,5µs. Este valor de tempoé menor do que o tempo permitido para não destruir o IGBT.

Os integrados também são capazes de gerar sinais de ocorrência de curto-circuito que podem ser transmitidos aocircuito de controle através de optoacopladores.

No circuito da Fig. 26, o sinal de ocorrência de curto circuito é transmitido para o circuito de controle por meio dosoptoacopladores CI2 e CI4. Neste circuito, o sinal de ocorrência permite a entrada em condução do tiristor de sinalSCR1 e coloca o pino 10 ( pino shutdown ) do circuito integrado CI-3524 (que no exemplo é utilizado para gerar ospulsos de comando) no potencial de tensão de VCC3, desta maneira inibindo completamente os sinais de saída docircuito integrado. No caso de não serem inibidos os sinais gerados pelo CI-3524, os circuitos integrados CI1 e CI3inibem os sinais de comando de gate por 1,2ms após detectada a falha e, logo após este intervalo de tempo, liberamnovamente o sinal de comando de gate e assim sucessivamente. Como os integrados CI1 e CI3 apresentam um tempo dereset, os optoacopladores CI2 e CI4 podem ser lentos.

.

1

2

8

7

6

R6

R7

Q3

Vcc3

Vcc3

Q2

R8

R5

C4 3

4

5

CI2

18

D1

C1

Z4

Z3

G1R3

C3

5

4C1

Vcc114

13

P1PinoShutdown

SCR1

R10

C5

R9

R1

Q1C2

6

CI1

Z2

R2

Z1Vcc2

E1

R4

1

2

8

7

6

R8R9

Q3

Vcc3

Q2

R10R7C4 3

4

5

CI4

18

5

4C1

Vcc114

R1

Q1

13 C2

C36

CI3

Z1

D1C2

Z4

Z3

G2R3

Z2

R2

Vcc2

E2

R4

R5

R11

vcon1

VGE1

vcon1

t

15V

vcon2

vcon2

t

15V

VGE2

R12

R6

6N136

M57962L

M57962L

6N136

Fig. 26 - Circuito de comando para braço utilizando dois circuitos integrados (CI1 e CI3) isolados com proteção de curto-circuito.Para a aquisição das formas de onda mostradas na Fig. 27 foi utilizado o circuito de potência da Fig. 9, onde os

interruptores IGBTs foram acionados com o circuito de comando para braço da Fig. 26. Todas as aquisições foramfeitas para uma freqüência de operação do interruptor igual a 25kHz.

Na Fig. 27 (a), são mostradas as formas de onda dos sinais da tensão de entrada Vcon e da tensão gate-emissor VGE.Esta figura foi adquirida para explicar o ajuste da desigualdade dos tempos de atraso do sinal de tensão gate-emissorVGE em relação ao sinal de tensão de entrada Vcon na subida e na descida. Neste caso, o tempo de atraso na subida é de650ns e na descida de 1,2µs. Esta desigualdade foi diminuída colocando-se um resistor de 270Ω em série com ofotodiodo na entrada do CI1 e CI2 (resistor R6 do circuito da Fig. 26). O excesso de corrente no fotodiodo faz com queo fototransistor fique excessivamente saturado aumentando o seu tempo de estocagem no bloqueio Nas Figs. 27 (b) e (c)são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon e da tensão de saída gate-emissor VGE com os ajustes necessários, para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada, na Fig. 27 (b),

o sinal de saída VGE apresenta um atraso na subida de 700ns e um atraso na descida de 700ns. Por outro lado, na Fig. 27(c) o sinal de saída VGE tem um atraso na subida de 650ns e um atraso na descida de 700ns. Com a modificaçãointroduzida, neste circuito, as diferenças dos tempos de atrasos na subida e na descida para toda a faixa de variação derazão cíclica estão dentro das especificações indicadas no catálogo do componente (M57962L).

Vcon

VGE

V

VGE

con

(a)Vcon e VGE[5V/div.;5µµµµs/div.] b) Vcon e VGE [5V/div.;5µµµµs/div.]

GEV

conV

VGE

IC

(c) Vcon e VGE [5V/div.; 5µµµµs/div.] (d) VGE [10V/div.; 10µµµµs/div.] IC [50A/div.; 10µµµµs/div.]

CEV

CI

(e) VCE [50V/div.; 10µµµµs/div.] IC [50A/div.; 10µµµµs/div.]

Fig. 27 - Formas de onda obtidos com os circuitos das Figs. 9 e 26.Na Fig. 27 (d) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor durante o teste

de curto-circuito do IGBT. Por outro lado, na Fig. 27 (e) são mostradas as formas de onda da tensão coletor-emissorVCE e da corrente de coletor durante o curto-circuito.♦ CIRCUITO C3

Na Fig. 28 é apresentado o circuito de comando utilizando o integrado TLP250 da Toshiba para acionar IGBTs eMOSFETs. Este circuito é isolado por meio de um optoacoplador interno composto de um diodo emissor de luz e umfotodetector integrado. O circuito permite aplicar pulso de tensão gate-emissor positivo de 15V e negativo de 5,1V. Ocircuito também realiza proteção de curto-circuito por detecção da tensão de dessaturação coletor-emissor, inibindo ospulsos de gate antes da destruição do IGBT. Uma outra característica do circuito é que permite a limitação da correntede curto-circuito por meio de redução da tensão gate-emissor após ocorrida a falha. Os dispositivos externos ao circuitointegrado são dimensionados de acordo com as limitações do circuito integrado TLP250. O circuito integrado TLP250 érecomendado para operar até freqüências de 25kHz pelo fato das diferenças dos tempos de atraso na subida e nadescida. Estas diferenças serão observadas nas Fig. 29.

Vcc1R2

Z5

Q3

Z2

R4

R3

Z6

R6

D4

D5C

Z4

R8

GD2

C4

Q1

Q2

R5

C3

Z3 EC2

VGE

D3

8

R1

1

2

3

4 5

6

7

Z1

CI1vcon

t

15V

TLP250

R7

C1

R9 D6 D7

C5

D1

Fig. 28 - Circuito de comando de gate isolado com proteção e limitação da corrente de curto-circuito.Nas Figs. 29 (a) e (b) são mostradas as formas de onda dos sinais de tensão de entrada do circuito de comando Vcon e

da tensão de saída gate-emissor VGE para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada, na Fig. 29 (a), osinal de saída VGE apresenta um atraso na subida de 400ns e um atraso na descida de 200ns, por outro lado, na Fig. 29(b) o sinal de saída VGE tem um atraso na subida de 400ns e um atraso na descida de 200ns. Este circuito apresentadiferenças nos tempos de atrasos da subida e da descida do sinal da tensão de saída. Para toda a faixa de variação de

razão cíclica, são iguais os atrasos.Na Fig. 29 (c) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor durante o teste

de curto-circuito do IGBT. Nesta figura, observa-se que quando ocorre o curto-circuito a tensão gate-emissor VGE éreduzida ao valor da tensão de operação do zener Z2 e, como conseqüência, a corrente de curto-circuito de coletor émantida em um valor de aproximadamente duas vezes o valor nominal. Desta maneira o interruptor é capaz de suportara situação de curto-circuito por um tempo muito maior que o tempo recomendado (10µs). Como pode-se observar, ointerruptor suporta 18µs sem ser destruído.

Na Fig. 7.29 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor durante aocorrência de curto-circuito do IGBT. Nesta aquisição é mostrado o detalhe do efeito da descida da corrente de curto-circuito que provoca uma sobretensão entre coletor e emissor devido às indutâncias parasitas do circuito de potência.Como a magnitude da corrente de curto-circuito é pequena em relação à magnitude de corrente em operação normal(sem limitação de corrente de curto-circuito), as sobretensões entre os terminais de coletor-emissor são muito pequenas.

VGE

Vcon

VGE

Vcon

(a) Vcon e VGE 5V/div.; µµµµs/div.] (b) Vcon e VGE [5V/div.; µµµµs/div.]

VGE

I C

VCE

IC

(c) VGE [5V/div.; 10µµµµs/div.] (d) VCE [50V/div.; 10µµµµs/div.]IC [50A/div.; 10µµµµs/div.] IC [50A/div.; 10µµµµs/div.]

Fig. 29 - Formas de onda obtidas com os circuitos das Figs. 8 e 28.

♦ CIRCUITO C4Na Fig. 30 é apresentado o circuito de comando dedicado SKHI22 da Semikron para acionar dois IGBTs em meia

ponte. Este circuito é isolado por meio de transformador de pulso. O circuito não necessita fonte de tensão no lado dasaída pois possui internamente um conversor cc/cc que gera as tensões complementares ±15V para os pulsos decomando do gate. Além disto, realiza ajuste de tempo morto através de sua lógica interna quando são aplicados pulsosde entrada sem tempo morto. O valor mínimo do tempo morto é de 2,7µs com possibilidade de ajuste acima do valorindicado. Os tempos de retardo dos sinais é em torno de 1µs na subida e 1µs na descida. O circuito apresenta proteçãode curto-circuito por detecção da tensão de saturação coletor-emissor VCEsat. O tempo de retardo de detecção de curtocircuito é 1,75µs para RCE = 24kΩ e CCE = 330pF (RCE e CCE são componentes externos ao integrado com os quais épossível ajustar este retardo, C1 e C2 , R4 e R9 da Fig. 30). Após este tempo de retardo o sinal de saída é inibido por 1µs.Em operação normal o pino de erro do circuito integrado encontra-se em nível alto (15V) e quando ocorre a falha emnível baixo (<0,7V). Quando ocorre a falha, os pulsos de entrada do circuito integrado devem ser inibidoscompletamente, pois se isto não ocorrer tem-se pulsos de curta duração na saída do circuito integrado que podemprovocar curtos-circuitos sucessivos do IGBT até destruí-lo. Os dispositivos externos ao circuito integrado sãodimensionados de acordo com as recomendações dadas no catálogo do fabricante do circuito de comando integrado.

O circuito integrado SKHI22 é recomendado para operar na faixa de freqüências de 5kHz a 100kHz. Ele apresentaum tempo morto de 2,7µs; por este fato pode não ser conveniente em algumas aplicações de freqüências elevadas.Quando o circuito de comando é aplicado em módulos de IGBTs de elevada capacidade de corrente de coletor IC, suafreqüência de operação é limitada pela carga da capacitância de entrada dos módulos.

Nas Figs. 31 (a) e (b) são mostradas as formas de onda dos sinais de tensão de entrada do circuito de comando VIN1e da tensão de saída gate-emissor VGE1 para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada VIN1, na Fig. 31(a), o sinal de saída VGE1 apresenta um atraso na subida de 1µs e um atraso na descida de 1µs, por outro lado, na Fig. 31(b) o sinal de saída VGE também tem um atraso de 1µs na subida e na descida. Neste circuito de comando os valores dosatrasos são praticamente iguais na subida e na descida, tal como indica no catálogo, para qualquer variação de razãocíclica. Nas Figs. 31 (c) e 31 (d) são mostradas as duas formas de onda de saída do circuito de comando. As mesmas sãocomplementares para acionar dois interruptores IGBTs de um mesmo braço de um conversor em ponte. O tempo mortoé ajustado acima do valor de 2,7µs através dos resistores R1 e R2 da Fig. 31.

Vcc1

CE1

C2

Z2

R5

R3

R6

E2

C1

Z4

G2

R9

R8

V

Z3

C2

G1Z1

ERROR

SKHI22 R1

R2

R10

C1

E1

R7

R4CE1C

ON1G

OFF1G

1E

2E

CE2V

CE2C

ON2G

OFF2G

GND/0V

SV

IN1V

TD1R

TD2R

IN2V

GND/0V

R11

R12

CI1

C3

Fig. 30 - Circuito de comando de gate isolado com proteção de curto-circuito.

VGE1

VIN1

VIN1 VGE1

(a)VIN1 e VGE1[5V/div;5µµµµs/div.] (b)VIN1 e VGE1 [5V/div;5µµµµs/div]

VGE1VGE2

VGE1

VGE1

(c)VGE1 e VGE2[5V/div;5µµµµs/div] (d)VGE1 e VGE2[5V/div;5µµµµs/div]Fig. 31 - Formas de onda obtidas com os circuitos das Figs. 9 e 30.

♦ CIRCUITO C4Na Fig. 32 é apresentado um circuito de comando muito simples para inversores, com uma utilização mínima de

componentes, utilizando transformadores de isolamento. Embora o circuito não tenha proteção de curto-circuito,permite aplicar uma tensão negativa durante o bloqueio e não necessita de geração de tempo morto.

Tr1

Lr

Cs

T1

D1

R2=47R

D2

R3=47R

Dz2

Dz3

Dz4

Dz5

T2

T3

+15V+Vcc

R1=2k2

D3

D4

Fig. 32 - Circuito de comando de gate isolado com transformador.O transformador de isolamento foi projetado para utilização com uma freqüência de comutação de 35kHz, utilizando

um núcleo da Thornton tipo E20, com 37 espiras de fio 28 AWG no primário e 40 espiras do mesmo fio em cadasecundário. O maior número de espiras no secundário (relação de transformação ligeiramente maior do que 1) permitecompensar as quedas de tensão do transistor T1 e do próprio transformador.

Para a aquisição das formas de onda mostradas na Fig. 33 os interruptores IGBTs foram acionados com o circuito decomando e de potência da Fig. 32. Todas as aquisições foram feitas para uma freqüência de operação do interruptorigual a 30kHz.

Na Fig. 33.a pode-se observar as tensões no enrolamento do primário e em um dos enrolamentos do secundário dotransformador. Na Fig. 33.b mostra-se as tensões de gate dos transistores T2 e T3 onde pode-se observar o efeito dacapacitância Miller, que varia com a variação da tensão VCE do IGBT.

a) Tensão nos enrolamentos b) detalhe da tensão de gateprimário e secundário dos interruptores na comutação

c) VCE1. [100V/div.; 2,5µµµµs/div.] e IC1 [0,5A/div.; 2,5µµµµs/div.]Fig. 33 - Formas de onda obtidas com o circuito da Fig. 32.

3 - CONCLUSÕESDepois dos testes realizados com os diferentes circuitos de comando mostrados anteriormente, chega-se à seguintes

conclusões:Os transformadores de pulso dos circuitos de comando de gate foram projetados para operar em uma freqüência de

comutação de 10kHz. Embora projetados para esta freqüência, ainda assim funcionam sem problema até freqüências deaproximadamente 40kHz. Porém, quanto maior for a freqüência, mais difícil será desmagnetizar o núcleo, devido aoelevado número de espiras (maior corrente magnetizante), aumentando os atrasos entre os pulsos de entrada e de saídado circuito de comando de gate. Recomenda-se projetar os transformadores de pulso, exatamente para a freqüência deoperação do conversor.

Em quase todos os circuitos de comando de gate projetados, os dispositivos que provocam maior atraso são ostransistores bipolares de sinal, pois o tempo de bloqueio destes transistores é elevado. Eles, para serem rápidos,necessitam da aplicação de uma corrente de base negativa (transistores npn). Por este motivo, para poder diminuir ostempos de atraso na subida e na descida dos circuitos de comando de gate, recomenda-se, se for possível, a utilização deMOSFETs de sinal.

Na prática todos os circuitos de comando de gate testados podem ser utilizados, pois eles apresentam boascaracterísticas de operação e confiabilidade. A escolha dependerá do critério do projetista do conversor, pois ele deveanalisar o tipo de isolamento necessário, em função da freqüência e da variação da razão cíclica. Algumas vezes ocritério de escolha também depende do custo dos componentes, volume e peso. As características de custo econfiabilidade não foram analisadas neste trabalho.

4 - REFERÊNCIAS BIBLIOGRÁFICAS[1] - FUJI ELECTRIC; "IGBT data book"; Catálogo; 1994.[2] - SEMIKRON; "Semicondutores de potência"; Catálogo, 1993; pp. A-67 à A-73.[3] - REINMUTH, K.; LORENZ, L.; "A new generation of IGBTs and concepts for their protection"; PCIM'94, June 28-30, 1994, Nürnberg-

Germany; pp. 139-147.[4] - ELASSER, Ahmed et al; “Switching losses of IGBTs under zero-voltage and zero-current switching”; IAS’96, San Diego, California, – U.S.A.;

1996; pp. 600-607.[5] - BALIGA, B. J.; "Modern power devices"; Ed: John Wiley & Sons, Inc., 1987; pp. 350-401.[6] - MARTINS FERNANDEZ, D. J.; "Conversor DC-DC quase-ressonante para altas potências utilizando IGBT"; Dissertação de Mestrado em

Engenharia Elétrica; Florianópolis, UFSC-Brasil; 1991.[7] - ELASSER, Ahmed et al; “Switching losses of IGBTs under zero-voltage and zero-current switching”; IAS’96, San Diego, California, – U.S.A.;

1996; pp. 600-607.[8] - CLEMENTE, S.; DUBHASHI, A.; PELLY, B.; " IGBT characteristic and application"; Application Note, AN-983A; 1994; pp. 93-106.[9] – BASCOPÉ, René Pastor Torrico; PERIN, Arnaldo José; "O transistor IGBT aplicado em eletrônica de Potência"; Editora Sagra Luzzatto,

Porto Alegre – RS, 1997.[10] - BISWAS, S. K.; BASAK, B.; RAJASHEKARA, K. S.; “Gate drive methods for IGBTs in bridge configurations”; IAS’94; 1994; pp. 1310-

1316.[11] - LETOR, R.; MELITO, M.; "Safe behavior of IGBTs subjected to dv/dt"; SGS-Thomson, Application Note, AN476/0492, 1994; pp. 715-723.[12] - SANTOS, A.; “Driving high current IGBTs in high-power circuits”, COBEP’95, 3rd Brazilian Power Electronics Conference, December 4 to 7,

São Paulo-Brazil, 1995; pp. 621-625.[13] - BARBI, I.; “Projeto de fontes chaveadas”; Publicação Interna, Florianópolis - UFSC - Brasil; pp. 31-58, 1990.[14] - BARBI, I.; ANDRADE, E. ;“Projeto e implementação de um inversor para cargas não lineares”; Relatório Interno, UFSC- Brasil, Março 1996.

1MOTOROLA

!

Prepared by: C.S. MitterMotorola Inc.

DEVICE CHARACTERISTICS

The recently introduced Insulated Gate Bipolar Transistor(IGBT) has been undergoing considerable improvement andmaturation due to improvement in process technology. Thisdevice has become the most popular new device used by thepower electronics design engineers. It is quickly replacingmost of the power BJTs because of its speed and ease of gatedrive. In this section, a brief overview of the device and itscharacteristics will be presented.

INTRODUCTION

In the power electronics arena there is a constant demandfor compact, lightweight, and efficient power supplies.However, the demands for the power converters are not fullysatisfied by power bipolar transistors (BJTs) and powerMOSFETs. High current and high voltage BJTs are available,but their switching speeds are not satisfactory. PowerMOSFETs have high speed switching, but high voltage andhigh current modules are not available.

The Insulated Gate Bipolar Transistor (IGBT) device is apower semiconductor device introduced to overcome thelimitations of the power BJTs and power MOSFETs. Thisdevice eliminates the high on–state losses of the MOSFETwhile maintaining the simple gate drive requirements of thatdevice. This device is controlled by the gate voltage as is thepower MOSFET, but the output current is that of a bipolartransistor. These devices combine the best features of boththe bipolar transistors and of the MOSFET.

In order to optimally implement all of the advantages of theIGBT device, it is essential that the designer understand thegeneral operating characteristics of the device.

DEVICE STRUCTURE

A schematic structure of an N–channel IGBT device isshown in Figure 1. The structure is similar to that of a VerticalDouble Diffused MOSFET (VDMOSFET) with the exceptionthat a p–type heavily doped substrate replaces the n–typedrain contact of the conventional VDMOSFET (see Figure 2).The p–type substrate is the emitter of the bipolar transistor andis the anode terminal of the device. When sufficient gatevoltage is applied, the current that flows at the surface of theMOSFET channel enters the low doped epitaxial layer andappears as a drain current at the substrate. In turn, the heavilydoped p+ substrate injects minority carriers into the low dopedn– epitaxial layer. The large n– area is needed in order to blockhigh voltages, but it contributes to a large on–state resistance.But the minority carrier injection by the p+ substrate serves to

reduce this resistance and thus modulates its conductivity.The injected minority carrier density is typically 100 to 1000times higher than the doping level of the n–type epitaxial driftregion.

Figure 1. Basic Structure of IGBT

Figure 2. Basic Structure of VDMOSFET

POLYSILICON GATE

N+

P+

N– EPI

N+ BUFFER

P+ SUBSTRATE

P–

Rmod

EMITTER

N+

P+

P–

COLLECTOR

GATE

NPN MOSFET

PNP

KEYMETALSiO2

bipolar emitter

bodyr′b

JFETchannel

Drain–to–Source Body Diode(Created when NPN

base–emitter is properlyshorted by source metal)

POLYSILICON GATE

N+

P+

N– EPI

N+ SUBSTRATE

P–

SOURCE

N+

P+

P–

DRAIN

GATE

NPN

KEYMETALSiO2

body

Order this documentby AN1540/D

SEMICONDUCTOR APPLICATION NOTE

Motorola, Inc. 1995

2 MOTOROLA

The minority carriers, which do not recombine as theydiffuse towards the body, are collected by the body–epitaxiallayer which is reverse–biased in the forward conductionoperation. The MOSFET channel is formed under the gatewhere the body meets the silicon surface, and this MOSFETprovides the electrons (majority carrier) for recombination inthe epitaxial layer and some are injected into the p–substrateregion (bipolar emitter). The n+ buffer layer is introduced forthe following reasons (we will not discuss it in detail in thispaper):

1. Limit injection of holes into n– region. This makes fasterdevices, but trades off forward drop.

2. Creates low lifetime region for recombination. This onlyaffects speed of non–irradiated devices.

3. Prevents punch–through of depletion region to p+substrate. This allows thinner epitaxial to be used whichlowers VCE(on).

4. Reduces PNP bipolar transistor gain which improveslatching and prevents thermal runaway of leakagecurrent at high temperature

5. Sets breakdown voltage of back junction

Much of the discussions presented have been EPI type or“punchthrough” IGBTs because the basic understanding ofthe device centers around the EPI type IGBTs.

IGBT Equivalent CircuitThe simplified equivalent circuit representing the internal

structure is shown in Figure 3. The circuit consists of anN–channel MOSFET, a PNP bipolar transistor, an NPN bipolartransistor, and a JFET. (This is a conceptual model and shouldnot be confused with the actual physical structure of theIGBTs.) The JFET is formed where the MOSFET current flowsbetween two adjacent body diffusions [1]. This JFET supportsmost of the voltage and is highly modulated giving theMOSFET its low RDS(on). This JFET is represented by themodulated resistor Rmod.

As shown in the model, the bipolar PNP and NPN form afour layer npnp structure of an SCR. If the gains of bothtransistors are significant enough, the BJTs will latch on andbehave just like an SCR. But this latching process is avoidedby the base–emitter short resistance, r ′b, in the equivalentcircuit. This resistance acts as a shunt to the base–emitterjunction of the NPN thereby preventing the NPN bipolartransistor from turning on strongly enough to start the latchingprocess.

Figure 3. IGBT Detailed Equivalent Circuit Showingthe Parasitic Components

PNP

EMITTER

GATE

COLLECTOR

NPN

r ′b

Figure 4. IGBT Detailed Equivalent Circuit Showingthe Parasitic Components

PNP

EMITTER

GATE

COLLECTOR

NPN

r ′b

Since the current to the base of the NPN bipolar transistoris bypassed, it can be assumed to be off, and this assumptionresults in the more simplified equivalent circuit as seen inFigure 4. This equivalent circuit only consists of a PNP bipolartransistor and the N–channel MOSFET. The simplifiedequivalent circuit clearly shows that the drain current of theMOSFET (electron current) supplies the base current of thePNP. The sum of electron current and whole currents make upthe total collector current of the IGBT device.

ADVANTAGES OF IGBT

Ease of Gate DriveAs discussed previously, the IGBT combines the best

features of the devices mentioned. It uses the low–power,voltage–driven gate drive to turn on and turn off, andpossesses a gate impedance as high as that of the powerMOSFET.

The structure of IGBT also reduces the reverse transfercapacitance, Cres, because a smaller chip area is required fora given current rating. This smaller capacitance results in avery low gate drive power requirement, since only a smallgate–drain capacitance charging and discharging current isrequired (this is one of the real benefits of the IGBT).

Low Conduction LossThe conductivity modulation of the n– layer greatly

increases the current–handling capability of the IGBT for agiven die size. This conductivity modulation has been shownto increase the forward conducting current density at givenanode voltage up to 20 times that of an equivalent MOSFETand five times that of a BJT [2]. Because this process reducesthe on–resistance of the device, the conduction loss isminimized. The disadvantage of conductivity modulation is theincrease in device switching time compared to the MOSFETdue to stored charge in the wide base region.

Positive Temperature CoefficientThe IGBT also has a favorable temperature coefficient for

on–resistance. At high currents the on–resistance increaseswith increase in temperature, and thus the device will notexperience the thermal runaway which occurs in the powerBJTs. (Note that under nominal and lower collector currentrange, the devices do have negative temperature coefficient.)It was shown that with increasing temperature, the currentsharing of the devices in parallel operation is improved [3].

3MOTOROLA

No Internal Anti–parallel DiodeThis can be advantageous or disadvantageous. With the

absence of antiparallel diode which is present in powerMOSFETs, IGBT can block reverse voltage (approximately–20 V); and with the use of series diode, reverse blockingcapability can be greatly increased. The absence of thisanti–parallel diode protects the IGBT from reverse conductionproblems in the free–wheeling diode, which can occur inpower MOSFETs. The designer has the freedom of selectingthe optimum rectifier if it is needed in a freewheelingapplication.

DISADVANTAGE OF IGBT

Current TailEven with many favorable qualities, the IGBT device

possesses a few unwanted characteristics; one is the slowswitching speed as compared to the power MOSFET. Whenthe device operates in forward conduction, the high resistanceregion n– epitaxial layer is highly modulated with injectedexcess minority carriers (conductivity modulation). When thegate voltage is removed, this excess of minority carriers mustbe removed before the device stops conducting completely.The turn–off speed of the device is determined by the integralbipolar open–base charge decay, and results in unwantedcurrent tail (see Figure 5). This slow switching contributes toa large switching energy and limited operation frequencies.The turn–on time is very fast and is determined by the rate ofon–voltage saturation of the integral PNP bipolar transistor.

Figure 5. IGBT Turn–Off Waveform

VCE

IC

CURRENTTAIL

CONCLUSION

The IGBT is a new power semiconductor device whichpossesses the best features of the both the MOSFET andbipolar transistor. The device is controlled by the samelow–power, voltage–driven gate as for the power MOSFETs,and the current handling is similar to that of BJTs. Whenoperating in forward conduction, its conduction loss isreduced by the conductivity modulation achieved by the highlevel of minority carrier injection from emitter toward the widebase region of the device. It has been shown that the currentdensity is 20 times that of power MOSFETs and five times thatof BJTs.

One disadvantage is the current tail during turn–off, and thisintroduces higher switching losses and limits the operatingfrequency of the device. At present, frequency of 25 kHz isobtainable without any special resonant switching technique.

4 MOTOROLA

IGBT GATE DRIVE CONSIDERATIONS

INTRODUCTION

Devices such as BJTs and thyristors require complicatedand very inefficient methods of driving the devices due to theirlow gain and minority carrier device characteristics. Inaddition, SCRs become difficult to control due to loss of gatecontrol during turn–off. But it is well known that MOSFETshave the simplest gate drive requirements of all the powerdevices mentioned. The device can be driven with low power,voltage pulses of required polarity. This simplifies the circuitdesign, and the switching characteristics can be accuratelycontrolled if all of the circuit parameters are well known.

Because IGBTs are much like fast MOSFETs during theswitching transitions, and these devices undergo high voltageand high current transitions, its switching characteristics mustbe understood by the design engineers in order to avoid someof the problems associated with high voltage and high currenttransitions. In order to give design engineers a thoroughoverview of the device characteristics, this section reviewssome of the switching characteristics within the clampedinductive load circuit. It is shown that the gate drive circuit,circuit layout, and external components play a vital part incontrolling the device switching under clamped inductive load.By understanding the device characteristics and the problemsassociated with rapid di/dt and dv/dt, the designer can avoidsome of the common problems.

This paper covers some of the fundamental switchingcharacteristics, and shows how critical the gate drive circuit isin determining the switching characteristics of the IGBTs.Some of the problems associated with rapid di/dt and dv/dt arediscussed, and suggestions are presented in order toovercome these problems.

The parameters that aggravate the problems associatedwith high di/dt and dv/dt have been shown to be DC businductance, common emitter inductance (common to gatedrive circuitry), large gate return loop area, the series collectorinductance, and the antiparallel diode of the clampedinductive load. All of these parameters contribute significantlyto the durability and longevity of the devices, and can affectoverall system efficiency.

TURN–ON

Because the IGBT is a MOS–gated device, the turn–onswitching performance is dominated by the MOS structure ofthe device. Figure 1 shows the clamped inductive load circuitused to analyze the switching characteristics of the IGBT. It isassumed that the inductor initially has a constant steady statecurrent flowing through it, freewheeling through the diode. Theinductance Ls is the series parasitic inductance due to thepower trace and any wiring between the IGBT’s collector andDC bus. The inductance Le is the common emitter inductanceseen by both the power return and the gate return.

Ideal switching waveforms describing the clampedinductive load circuit are shown in Figure 2. During the timeperiod t0, the gate current charges the constant inputcapacitance (Cies) with a constant slope, and as is the casewith the MOSFET, nothing happens until the gate–sourcevoltage is raised to the threshold voltage Vth of the device.During t1, the collector current is redirected from the diode intothe device and increases to its steady state value. The current

slope is dependent on gate voltage rise time and deviceforward transconductance. The following expression can beused to express the current slope:

dICdt

gmdVGE

dt. (1)

The time rate of change in gate–emitter voltage during t1period is given by:

dVGEdt

(VGG – Vplateau)

RG Cies, (2)

If we substitute equation 4 into equation 1, the rate ofchange of collector current is expressed as:

dICdt

gm(VGG – Vplateau)

RG Cies. (3)

Figure 1. Clamped Inductive Load

DC SUPPLY

DC RTN

IGBT

LOADIL

RG

VGG

Ls

Le

Figure 2. Idealized Turn–on Switching of IGBT

t0 t1 t2 t3

VGE

IC

VCE

t

t

5MOTOROLA

During the plateau region t2, the gate–emitter voltage hasreached the value which will support the steady state collectorcurrent, and the collector–emitter voltage starts to decrease.During this region, gate drive current is discharging thevoltage–dependent reverse transfer capacitance at aconstant gate current that can be expressed as:

ig (VGG – Vplateau)

RG Cres

dVCGdt

. (4)

where, Vplateau Vth ICgm , (5)

and gm is the forward transconductance of the device at thegiven steady state collector current IC and can be obtainedusing the transfer curve provided by the data sheets.Transconductance is determined by steady state collectorcurrent divided by the intercepting gate voltage (IC/VGE, seeFigure 3). It should be noted here that the above analysisignores the change in bipolar current gain as base charge issupplied.

The parameter for input capacitance Cies can be obtainedusing the capacitance curve provided by the device vendors.Figure 4 is a sample curve indicating the capacitance valuesfor input, output, and reverse transfer capacitance Cres. Abetter method of obtaining the capacitance would be to usethe gate charge transfer curve. By using the amount of chargeneeded to turn the device on at a certain operating point, moreaccurate assessment of gate drive current can be determined.A sample of a gate charge curve for an IGBT is shown inFigure 5, but for qualitative results the curve given by Figure4 is adequate.

All of the above expressions are presented to show therelationship between the series gate resistance and its effecton the rise time of the device current. Using these equations,the designer can control the current and voltage slope duringturn–on. During region t3 the dynamic switching is completed,and a further increase in gate–emitter voltage has no effect onthe dynamic characteristics. But, as we will discuss later, thefinal gate–emitter voltage determines how much turn–on lossis expended by the circuit and determines the magnitude andduration of short circuit current handled by the device.

Turn–On Switching ConsiderationsIn order to reduce the dynamic turn–on loss, the switching

time must be very short. This requires that the gate drive bea low impedance type, and be able to provide a large narrowpulse of current to charge the input capacitance whichincludes the feedback capacitance and gate–emittercapacitance. The turn–on switching time is determined by howquickly the input capacitance Cies is charged. However, thefast switching speed will introduce high di/dt (maximum di/dtis a function of load inductance and the gate drive: 1) whereinitial di/dt = V/L, and once inductance has charged to itsmaximum load current, 2) the di/dt will be dominated by thegate drive) which will interact with the lead inductance of theemitter. The control of turn–on di/dt can be seen by observingequation 5. In this equation it is evident that by changing thegate resistor value, the rate of the rise of the device current canbe increased. This large di/dt will induce large enoughtransient voltage across the common emitter inductance andwill reduce the available gate voltage causing linearization of

the initial collector current rise because of its gate currentlimiting while increasing the turn–on loss [4]. In order toovercome this problem, a small gate resistance is placed inseries with the gate of the device, but remember that theinductance seen by the gate must be minimized. Placing thecomponents as near as possible to the gate–emitter terminals,along with good circuit layout, will reduce much of theunwanted inductance. Also, the gate–emitter current loopmust be short. It is good practice to use twisted wire or parallelpower paths. Overlapping the power and return paths of thegate drive has the advantage of nullifying magnetic fieldinduced by power trace with the magnetic field induced by thereturn trace and the effective loop inductance is minimized.

40

30

20

10

0111098765

VGE, GATE–TO–EMITTER VOLTAGE (VOLTS)

I C, C

OLL

ECTO

R C

UR

REN

T (A

MPS

)

Transfer Characteristics

Figure 3. Gate–Emitter Voltage Due toTemperature Variation

25

GATE–TO–EMITTER OR COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)

Figure 4. IGBT Capacitance Curves

20151050

C, C

APAC

ITAN

CE

(pF)

4000

3200

2400

1600

800

0

Capacitance Variation

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

VCE = 100 V5 µs PULSE WIDTH

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

TJ = 125°C

ÁÁ

ÁÁ

ÁÁ

ÁÁ

25°C

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

VCE = 0 V

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

TJ = 25°C

ÁÁ

ÁÁ

ÁÁ

ÁÁ

Coes

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

Cies

ÁÁ

ÁÁ

ÁÁ

ÁÁ

Cres

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

6 MOTOROLA

Gate–to–Emitter and Collector–to–EmitterVoltage versus Total Charge

80

Qg, TOTAL GATE CHARGE (nC)

Figure 5. Gate Charge Transfer Curve

16

12

8

4

06040200

V GE,

GAT

E–TO

–EM

ITTE

R V

OLT

AGE

(VO

LTS)

ÁÁ

ÁÁ

ÁÁ

ÁÁ

VGE

ÁÁ

ÁÁ

ÁÁ

ÁÁ

QTÁÁ

ÁÁ

ÁÁ

ÁÁ

Q1

ÁÁ

ÁÁ

ÁÁ

ÁÁ

Q2

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

TJ = 25°CIC = 20 A

Rapid di/dt not only limits the available gate voltage, butcauses the bus voltage to dip, or decrease due to Ls(di/dt),where Ls is the stray inductance of the power DC bus. Duringturn–off, the rapid di/dt will cause a large positive voltage to beseen by the device which can exceed the rating of the device.Therefore, it is important to reduce di/dt during turn–on andturn–off duration. A local bypass for the DC bus should beprovided as near as possible to the device with a high current,low ESR capacitor. Without these precautions the IGBT mayencounter avalanche breakdown due to di/dt inducedtransient during the turn–off time.

Effect of the Freewheeling Diode Just as during turn–off, a surge can occur during the

recovery of the freewheeling diode. For high di/dt, the reverserecovery of the diode can become very snappy. Because ofthe stray inductance within the circuit and the device leads,this large di/dt will cause a large dv/dt once the diode isrecovered. The high di/dt caused by the snappy recovery ofthe diode can cause large unwanted voltage transients.Therefore, proper choice of the freewheeling diode isabsolutely critical in the performance of the device. A snappyrecovery can be controlled or eliminated by increasing thegate resistance RG, but this will increase the turn–on time, andthe efficiency of the circuit will suffer. Therefore, an ultrafastdiode with a soft recovery must be chosen. Otherwise asnubber must be used to control the snappy recovery of thediode.

TURN–OFF

The turn–off of the IGBT is initiated by removing the voltageacross the gate–emitter just as for MOSFETs. Figure 6 showsidealized turn–off waveforms for switched inductive load. Thefirst part of the turn–off process is the delay time (td(off)), whichis the effect of the time required for the gate drive to pull VGEfrom its full value to the level at which the collector voltagebegins to increase. Nothing is observed while gate voltage isdecreased, until the gate voltage reaches the value requiredto keep the collector steady state current to flow. During t5, the

collector voltage rises, and its rate of rise can be controlled bythe gate resistance RG:

dVCEdt

VplateauCres RG

. (6)

Equation 6 assumes that the gate resistance is largeenough that the output capacitance is not the limiting factor.

Figure 6. Idealized Turn–off Switching for IGBT

VGE

IC

Vth

VCE

t

t

tdelay

t4 t5 t6 t7

CURRENTTAIL

At t6, the collector voltage has reached the bus voltage VDD,the freewheeling diode starts to conduct, and collector currentstarts to decay. Because of the high di/dt, the collector voltagerises beyond the bus voltage due to L(di/dt) overshoot. Theregion, t6, is the initial fall time, and this is the time required forthe gate drive circuit to remove the charge that flows into thegate from the gate–to–drain capacitance as VDS increasesduring turn–off. This period is greatly influenced by the gatedrive design and its drive impedance, RG. For small gateresistance, period t6 is determined by the clamp inductance.This period is defined as the time it takes for Ic to drop from90% of its full current down to approximately the 10% level(this will include the tail). This period is greatly influenced bythe gate drive design and its drive impedance, RG, and theeffect of RG on the collector current fall time is expressed as:

dICdt

VplateauRG Cies

. (7)

The time period t7 shows an abrupt decrease in currentslope. This current slope is due to the recombination of theminority carriers in the wide base region of the integral BJT.This recombination process produces what is frequentlytermed as the “current tail.” This current tail limits the operationfrequency of the IGBTs, and the size and length of this currenttail is determined by the device design and processtechnology.

7MOTOROLA

Turn–Off ConsiderationsJust as with the MOSFETs a negative bias can be applied

to the gate in order to speed up the turn–off. This does notmean that the recombination of minority carriers in the widebase region will be increased, but it helps to speed up theturn–off of the MOSFET portion, and thus turns off the base ofthe integral PNP bipolar transistor quicker. The rapid turn–offwill cause a high dv/dt.

The problem associated with high dv/dt is that it canintroduce current through the capacitance to the base of theinternal parasitic NPN bipolar transistor (only in a bad device),thereby causing the device to latch on. Once the device islatched on, the gate–control is lost and the device cannot beturned off without removing the power to the collector terminalof the device (see Figure 2). A small gate–emitter resistancecan be added to the terminals to bypass the dv/dt problem.Also a series resistor should be used when negative gate biasis applied during the turn–off process. The negative biasshould be left on while the device is turned off. This will protectthe device from the false turn–on due to the dv/dt problem.Optimum values of the resistors can be found by tryingdifferent values of the resistor in the circuit to be used or bysimulation.

Effect of the Current TailThe t7 interval, as discussed earlier, is a result of minority

carrier recombination in the bipolar PNP structure. IGBT is aminority carrier device during the forward conduction, and assuch the highly resistive region (n– epitaxial layer) is highlyinjected with minority carriers. This minority carriers must beremoved before the device stops conducting completely. Theturn–off speed of the device is therefore determined by theintegral bipolar open base turn–off. This tailing effect is thedirect result of the internal base of the PNP structure whichcannot be accessed by the external means; and as a result,we cannot discharge the excess minority carriers by reversebiasing the gate. The controlled rate at which the minoritycarriers recombine is a function of device design and processtechnology. This current tail contributes to limit operationalfrequency and introduces large switching energy to bedissipated by the device. How fast the minority carriersrecombine determines how long the current tail is and theturn–off speed of the device.

GATE DRIVE REQUIREMENTS

From the previous discussion of switching characteristics ofthe IGBT, the following have arisen as the important factorsthat need to be considered when designing the gate drive:

1. Reduce the gate–emitter current loop by separating thepower return and gate return

2. Use a twisted wire if possible and overlap the powertraces of gate drive if PCB is used

3. Make the gate drive connection as short as possible tothe device being used so as to reduce any parasitics

4. Use a series gate resistor, RG to limit di/dt and dv/dt

5. Use a negative bias if possible to reduce any dv/dtproblems

CONCLUSION

IGBTs are excellent candidates for high power applications.However, when switching high voltage and high current, caremust be taken in the beginning stage of the design to ensurethat circuit layout will support the high di/dt and dv/dt. Someequations have been provided so that by using appropriategate resistors, di/dt and dv/dt can be controlled.

It was observed that the gate drive is a vital element inobtaining the maximum performance of the device. Throughthe correct use of gate drive the designer can overcome someof the common problems associated with high voltage highcurrent switching: 1) accurately control di/dt and dVCE/dtproblems, and 2) avoid latching of the parasitic thyristor. Usinga negative bias at the gate reduces the chance of false turn–onand latching of the device. Not only was the gate drive vital indetermining the switching loss, but the freewheeling diode ina clamped inductive load introduces turn–on switching losses.It is of utmost importance that an ultrafast diode with softrecovery type be chosen.

Layout of the circuit was vital in overcoming some of theswitching problems. The ground loop of the gate drive must beseparated from the power return so that the common emitterinductance does not interrupt the turn–on process. Thetwisted wires or parallel power tracts should be used for thegate drive. In order to reduce any unwanted supply businductance, it was suggested that a bypass capacitor with lowinductance and low ESR be connected right at the devicelevel, or just as in gate drive, the supply bus tracks can beparalleled. By following some of these recommendations,many of the common problems associated with high currentand high voltage switching can be dramatically reduced.

8 MOTOROLA

EFFECT OF GATE–EMITTER VOLTAGE ON TURN–ON LOSSAND SHORT CIRCUIT CAPABILITY

INTRODUCTION

Unlike the MOSFETs and BJTs, the magnitude of thegate–emitter supply voltage of an IGBT has a significantimpact on the performance of the device. The magnitude ofthe gate voltage impacts the turn–on loss and short circuitsurvival capability of the devices. In this section some of theimpacts of the gate–emitter voltage on the deviceperformance will be examined.

TURN–ON LOSS

As mentioned before, the turn–on characteristics of IGBTsare similar to those of a MOSFET. In MOSFETs, once thegate–source voltage has reached the value to support thesteady–state drain current, a further increase in VGS has nosignificant role in the circuit, but it does greatly affect theswitching speed of the device. The magnitude of thegate–emitter voltage significantly affects the magnitude of theturn–on loss during the transition.

Figure 1 depicts measured data that shows the relationshipbetween gate–emitter voltage and turn–on loss with aconstant RG, 20 ohms. As shown by the curves, largergate–emitter voltage reduces the turn–on loss of the device.This can be explained by the fact that for a given gate resistor,the gate current available increases with the increase in thegate voltage. Therefore, the input capacitance of the device ischarged at a faster rate which can account for less loss. Thelonger it takes the device to turn on, the more energy isdissipated by the device. For given collector currents,increase in gate–emitter voltage reduces turn–on loss.

50

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25

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15

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Figure 1. Turn–on Loss with DifferentGate–Emitter Voltage

E on

, (N

OR

MAL

IZED

)

RG = 20 OHMS

20 V

17 V

15 V

12 V

SHORT CIRCUIT FAULT OPERATION

A major concern in inverter applications is the ability tosurvive a short circuit fault condition. During the short circuitfault, the device is exposed to the supply voltage across the

device, while the gate potential is at full operating value (seeFigure 2). Because of the high gain characteristic of the IGBTs,the collector current will rise to some undetermined valuelimited by the gate–emitter voltage. During this time the devicewill have a large amount of energy across the device, and if theenergy is beyond the capability of the device it will bedestroyed due to thermal breakdown. For the bad devices, thelarge current can cause parasitic NPN bipolar transistor to turnon and cause the device to latch, wherein the gate control willbe lost.

One point to note here is that the IGBTs are less sensitiveto second breakdown due to hot spot formulation unlike theBJTs. In understanding this, it is clear that the device shouldbe able to survive a short circuit condition if the energydelivered to the device is maintained below some value thatis tolerable to the device.

There are many different ways to protect the device from theshort circuit condition for some duration. Remember that thedevice does not turn off when a short circuit occurs, but ratherlimits the amount of the energy dissipated by the device bylimiting the collector current. This provides enough time for theexternal protection circuits to be activated. Therefore it is ofutmost importance that the device be able to survive a shortcircuit fault condition. The most effective way to provide theshort circuit survivability would be to inherently build currentsensing capability into the device, but as of now, nomanufacturer has any device which has built–in current sensefor short circuit detection. IGBTs produced by Motorola arecapable of short circuit survivability of 10 µs minimum.

Another method of increasing the short circuit survivabilityis to decrease the gate voltage when the short circuit acrossthe device is observed. Figure 3 data shows the relationshipbetween the gate voltage, short circuit current, and the shortcircuit survival time period. As shown in Figure 3, it is clear thatthe smaller gate voltage limits the current at lower value andincreases the short circuit time duration.

Figure 2. Equivalent Short Circuit Condition

SHORT CIRCUITFAULT

VDDVGG

9MOTOROLA

80

60

40

20

02019181716151413121110

VG IN VOLTS

Figure 3. Short Circuit Response of IGBT

I SC

IN A

MPS

40

30

20

10

0

t SC

INµ

ISC

tSC

Short Circuit Time & Currentversus Gate Voltage

s

SUMMARY

IGBTs are high current and high voltage devices. Becauseof their use in high power applications, it is important that someof the key behavior of the device is understood by the user inorder minimize switching losses and to prolong their lifetime.

In most cases, the turn–on loss of the device in a clampedinductive load is dependent on the performance of thefree–wheeling diode, and is a function of the diode’s reverserecovery time. But as we have discussed, the magnitude of thegate–emitter voltage can be optimized in order to reduce theturn–on loss of the device. But on the other hand, the designerneeds to understand that the high gate–emitter voltagereduces the short circuit survivability of the device.

Using these two relationships, the designer can choose thebest voltage value which will meet their design requirements.

10 MOTOROLA

FORWARD CONDUCTION AND TURN–OFF BEHAVIOR OF IGBTS AT HIGHTEMPERATURE AND ITS CONTRIBUTIONS TO STATIC AND DYNAMIC TURN–OFF LOSS

INTRODUCTION

IGBTs have been introduced to overcome the high on–statevoltage of MOSFETs and slow switching frequency of BJTs.But because IGBTs possess dual device characteristics, theirbehavior is not easily understood. In high current applications,the on–state voltage becomes a major issue, and, in othercases switching losses may be the major concern. In thissection the on–state voltage characteristics and dynamicturn–off will be discussed. It is shown that the uniquecharacteristics of the IGBTs allow the designer to operate thedevice to obtain low conduction loss. But also shown are thatdynamic turn–off losses must be taken into consideration withvariation in temperature.

During the turn–off at high temperatures close attentionmust be given to: 1) current tail variation, 2) initial currentheight of the anode current, 3) reduced rate of rise of anodevoltage, 4) and increased carrier lifetime. All of these add tothe turn–off energy loss and can damage the device if care isnot taken.

FORWARD CONDUCTION

Because IGBTs behave like MOSFETs in switchingtransitions, it can be misunderstood that the device alwayspossesses a positive temperature coefficient (that is, theon–voltage increases at higher temperature). This perceptionis partially correct. As we shall see the device actuallypossesses negative temperature coefficient at low currentlevels.

60

40

20

086420

VCE, COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)

Figure 1. IGBT Output Characteristics

I C, C

OLL

ECTO

R C

UR

REN

T (A

MPS

)

VGE = 20 V

TJ = 125°CTJ = 25°C

IGBTs possess aspects of both MOSFET and BJTcharacteristics. Figure 1 shows the temperature dependenceof collector current versus collector–emitter voltage. For lowcurrent levels, the device possesses a negative temperature

coefficient, and as a result the saturation voltage is decreasedwith increase in temperature. At some current level, the twocurves cross each other and at this crossover point VCEbecomes temperature independent. At higher current levels,the device possesses a positive temperature coefficientcharacteristic and its saturation voltage increases withincrease in temperature.

At high temperature, there are a few important things thatare happening which contribute to the device on–voltage. Itwas discussed by Hefner [5] that: 1) the base resistanceincreases with temperature due to decrease in the mobility ofthe carriers, 2) emitter–base junction diffusion voltagedecreases due to increase in base intrinsic carrierconcentration, 3) the drain–source voltage increases slightlywith temperature because the decrease in MOSFETtransconductance dominates the decreasing thresholdvoltage for the high gate voltage bias condition.

The on–voltage of the device decreases with temperatureat lower current levels because the base resistance andchannel resistance is small compared to the change inemitter–base junction diffusion voltage. The BJTcharacteristics of the device are dominating at this point. Butfor higher current levels, the base resistance and channelresistance start to become significant enough and dominatethe on–voltage of the device, and as a result, introduce thepositive temperature coefficient which is a MOSFET effect ofthe device.

If the operating current is within the negative temperaturecoefficient region, one can be mistaken in thinking thatoperating the device at a higher temperature will be muchmore efficient. This may be true if other factors such asconduction current, thermal environment, circuit layout, andother operating parameters have been considered. But as wewill later see, dynamic turn–off must be considered at hightemperature operation

TURN–OFF

Unlike the relatively temperature insensitive forwardvoltage drop of the device, the turn–off energy loss isincreased with temperature. Figure 2 shows the dramaticincrease in turn–off loss at high temperature. This increase inenergy loss is contributed largely by the increase in the currenttail. The current tail is a function of the base minority carrierlifetime and is increased with rise in temperature. Not only iscurrent tail length increased, but the storage time, dVC/dt, andinitial anode current tail height is also increased. These effectsall contribute to higher turn–off energy loss, and attentionshould be given by the designers using the IGBTs. Byunderstanding how the device behaves with the temperatureat turn–off, the design engineer can better assess the bestoperating parameters for a given application.

11MOTOROLA

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E off

(NO

RM

ALIZ

ED)

Figure 2. Turn–off Energy Loss at DifferentTemperatures

ÁÁ

ÁÁ

ÁÁ

125°C

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

25°C

Turn–off Losses versus I C

Current TailWith an increase in temperature, the mobility of the minority

carriers in the wide base is reduced, and the lifetime isincreased which prolongs the current tail during the turn–off ofthe transistor. The increase in the current tail can account foralmost 60% of the turn–off loss. Not only is more energydissipated by the device, this will reduce the operatingfrequency of the device. Figure 3 depicts the anode currentduring the turn–off. The initial current height is denoted byIT(0+) and is the time at which the current tail starts to decayexponentially. For devices which do not have the buffer layer,the initial height of current tail remains relatively constant andwith temperature only current tail length is increased. But fordevices with the buffer layer, this initial tail height increaseswith the temperature. Both the increased height and length oftail with temperature means that the device will turn off slower.

It was discussed that the IT(0+) is proportional to the basecharge Q, and diffusivity of the device [6]:

(1)IT (0+) ∝ Q ⋅ D

IT (0–)

IT (0+)IF

TIME

ANO

DE

CU

RR

ENT

Figure 3. Anode Current During Turn–off

For nonbuffered devices, the increase in the base chargewith temperature is negated by the corresponding decreasein the diffusivity. But in the buffered devices, the increasedcharge due to the temperature is greater than the decrease inthe diffusivity of the device, and as a result, the initial currentmagnitude varies with temperature. The variation in initialcurrent height and in current tail length is the major contributorto the turn–off energy loss.

Figures 4 and 4b show turn–off waveforms at two differenttemperatures. The data shows that the initial current heightand current tail is increased significantly at highertemperatures. This increase in the current tail length and initialcurrent height contributes to a larger turn–off energy loss.

Figure 4a. Turn–off Waveforms at 25 °C

Figure 4b. Turn–off Waveforms at 120 °C

IC

CURRENT TAIL

VCE

VCE:VGE:IC:TIME:

50 V/div5 V/div2 A/div250 ns/div

VGE

VCE

IC

VGE

VCE:VGE:IC:TIME:

50 V/div5 V/div2 A/div250 ns/div

Initial CurrentTail IncreasedDue to IncreasedTemperature

Collector Voltage TransitionsIn the previous paragraphs it has been discussed how the

increase in device temperature decreases the mobility andincreases the lifetime of a device. This increase in lifetime alsoincreases the current tail length and its associated initialcurrent height. But as we shall see, the rate of rise of the anodevoltage is also affected by the temperature due to increase inthe lifetime, and adds to total turn–off loss.

12 MOTOROLA

Figure 5 shows an equivalent schematic of IGBT showingall of the internal circuits associated with the device. Duringthe turn–off, the output capacitance is dominated by thecollector emitter redistribution capacitance, Ccer. Thiscapacitance is orders of magnitude larger than the depletioncapacitance and dominates the effective output capacitanceof the IGBT during turn–off. Because this capacitance ischarge dependent, its value is varied with change intemperature (charge is varied with temperature). At hightemperature, the increase in charge increases the effectiveoutput capacitance and thus decreases the rate–of–rise of thecollector–emitter voltage. The following equation can beexpressed as:

Ibase Q

THL. (2)

Current Ibase is a steady state current level, charge Q ischarge present in the base, and tHL is the excess carrierlifetime. With increase in temperature, the whole lifetime isincreased due to reduction of mobility of carriers within thebase region. The increase in the base lifetime means that thecharge must increase in order to provide the unchangedcollector current. During the voltage transition, the effectiveoutput capacitance and rate–of–rise of the anode voltagemust be able to supply the steady–state collector current.Since the capacitance is proportional to the amount of chargepresent, its value is increased accordingly. Largercapacitance then decreases the rate–of–rise of the anodevoltage because it takes longer to charge the biggercapacitance. The rate–of–rise of the collector voltage is aninverse function of the capacitance, and the followingexpression can be used to describe its dependency on chargeand capacitance:

dVCdt

1

Ccer

1Q

(3)

Figure 5. IGBT Equivalent Circuit Superimposed onOne–half of Symmetric IGBT Cell

(Reprinted with permission from NIST)

CATHODE GATE

Cm

Coxs MOSFET Coxd

Cgdjsn+

p+c

Ccer

n–

p+

Cdsj db

RbBJT

ANODE

e

Cebj + Cebd

Ads Agd

DepletionRegion

Storage TimeOther side effects of the decrease in the rate–of–rise of the

voltage is that it prolongs the storage time. In a clampedinductive load, the collector voltage must reach its full supplyvoltage value before the collector current starts to decay (seeFigure 5). The decrease in dVCE/dt causes the collectorcurrent to remain at its full steady–state value much longer,and hence increases the turn–off loss.

FURTHER DISCUSSION ONTEMPERATURE EFFECT

Figure 6 shows all of the phenomenon that has beendiscussed previously. The first thing to note is that the initialcurrent tail magnitude has increased dramatically. But alsonote that the storage time has been increased due to thedecrease in dVCE/dt. As shown in Figure 6, dVCE/dt isdecreased by a factor of two, and is independent of gatevoltage after t6 region (it is assumed that there is no significantvariation in gate drive performance with variation intemperature). Notice the lack of voltage overshoot due todecrease in the slopes.

Figures 7 and 8 are measured data showing the effect oftemperature variation during the turn–off. All of thephenomenon discussed are apparent during the turn–offtransition. One important factor to remember is that the devicewas operated only at 50% of its rated voltage. If the collectorvoltage is increased, the turn–off loss encountered canincrease much more which will then increase the junctiontemperature of the device. (See Figure 9.) So special careshould be given to the turn–off transition if the device is tooperate efficiently under temperature variations.

VGE STORAGETIME

125°C

25°CVth

t

t

IC

25°C VCE

125°C

CURRENTTAIL

t5t4 t6

t7

Figure 6. Turn–off Behavior of IGBT withTemperature Variations

13MOTOROLA

Figure 7. Turn–off at 25 °C (VDD = 300 Vdc)

IC

VCE

VCE:VGE:IC:TIME:

50 V/div5 V/div2 A/div25 ns/div

Figure 8. Turn–off at 120 °C (VDD = 300 Vdc)

IC

VCE

VCE:VGE:IC:TIME:

50 V/div5 V/div2 A/div25 ns/div

VGE

Figure 9. Turn–off at 120 °C (VDD = 500 Vdc)

ICVCE

VGE

VCEVGE:IC:TIME:

100 V/div5 V/div2 A/div25 ns/div

CONCLUSION

IGBTs have very unique characteristics which can beutilized to best meet many of the high power switchingapplications. But unlike BJTs and MOSFETs, it is notstraightforward when it comes to designing for temperaturevariations. One must not only look at the on–state voltage, butone also needs to consider the dynamic behavior of the devicewith temperature. How well the device temperature isstabilized determines how rugged the device will be. If theenvironment is such that temperature variation is minimal (andcan be guaranteed), the design can be optimized for theon–state voltage because the turn–off energy loss variationswill be small. But if the temperature stability is not guaranteed,the designer needs to consider all of the parametersdiscussed and great care should be given to device junctiontemperature. The design should be done by derating the partfor the worst case condition which the device will confront. Ifcare is not taken, one can be assured of device failure ordegraded performance. The following are some of theconsiderations that should be taken when using IGBTs:

1. Temperature environment of the circuit2. Device characteristics with temperature variations3. Increase of storage time4. Decrease of dVC/dt5. Increase in initial current tail height6. Increase in total current tail length7. Operating current of the device8. Operating frequency

Considering these factors will help the design engineers tobetter utilize all of the benefits of IGBTs.

14 MOTOROLA

IGBT PARALLELING CONSIDERATIONS

INTRODUCTION

Paralleled IGBTs are used extensively in power modules toobtain higher current ratings [3], thermal improvements, andfor redundancy. However, the typical process variation ofdevice parameters within a given device type is significantenough to result in uneven static and dynamic current sharingif the paralleled devices are chosen randomly from a given lotof IGBTs of the same type. Design engineers must make surethat the temperature variations do not significantly vary thesignificant device parameters, and caution must be observed.Aside from the temperature and device parameter variations,it is well known and much has been written about how thecircuit layout and its contribution can greatly influence theperformance of devices in parallel operation.

In this section the characteristics of IGBTs under paralleloperation are shown. The effect of device parametervariations under static and dynamic current sharing arestudied, and the effect of temperature and circuit layout arediscussed. Then some suggestions are presented on how toovercome the common problems associated with parallelingIGBT devices. It is shown that if the designer considers carefulcircuit layout, thermal considerations, and pays carefulattention to process variations within the given lots, many ofthe problems associated with the paralleling power IGBTdevices can be avoided.

Many of the papers written about parallel operations ofIGBTs concern the effect of temperature variations. It is truethat temperature is the key role player in the destruction ofIGBT devices. But it is unclear as to what or how thetemperature is changing the device characteristics. TheIGBTs have the dual device (MOSFET and BJT)characteristics, and in order to truly understand thetemperature effect on paralleling, it is necessary tounderstand how the temperature changes the characteristicsof each device type. In this way the designer is better informedand will be able to better design for “key” parameters.

PARAMETER VARIATIONS

In order to observe how the dissimilar parameters affectcurrent sharing of the paralleled IGBTs, the parameterslifetime tHL, threshold voltage Vth, and transconductance Kp,were varied between two different devices. These parameterswere chosen because the normal process variation of theseparameters has the most impact on current sharing for paralleloperation [7].

The circuit used to simulate and test the parallel operationof IGBTs is shown in Figure 1.

The inductors LS1, LS2, Le1, and Le2 are the inductancesdue to lead and power traces. The load resistor RL is used tolimit the collector current to a safe level. It is shown that theseparasitic components have a significant role in the operationof the IGBTs.

Variations in LifetimeThe effect of lifetime on the IGBT is through the bipolar

characteristics of the device. In order to understand how thelifetime variation behaved in parallel operation of IGBTs, twodevices with dissimilar lifetimes were observed. Figure 2shows a waveform of collector voltage and collector current ofboth device types. The difference in lifetime has no effect on

VGG

RG1 RG2

LOAD RL

Q1 Q2

Le2Le1

Ls1 Ls2

DC SUPPLY

DC RTN

Figure 1. Paralleled IGBTs Used in Inductive Load

turn–on transitions, but the current imbalance during thesteady–state region, and turn–off variations are observed.The device with the higher lifetime conducted more currentthan the device with lower lifetime. Because of this higherlifetime, more charge is stored in the wide base region, andthus decreases the saturation voltage. With its lower VCE(sat),it draws more of the load current. No significant current spikeis observed during the turn–off transition, but as expected thedevice with higher lifetime had a larger current tail becausemore charge had to be removed.

Figure 2. Paralleled Operation of IGBTs withLifetime Variation

HIGHLIFETIME

LOWLIFETIME

VCEIC1

IC2

Temperature Effect on the Lifetime Variations. Withincrease in temperature the lifetime increases. Figure 2 showsthat if the static current sharing is within the tolerable region,there is no problem associated due to lifetime variations.During the turn–off sequence, the length of the current tail ofthe device with higher lifetime is increased. This increase incurrent tail will increase the turn–off loss of that device butshould not have significant effect on the static current sharingif the parameter variation is minimal. But if the devices havewide variation in the lifetime, the device with the higher lifetimecan encounter thermal breakdown (for example, paralleling anultrafast IGBT with a slow IGBT). The thermal effect of thedevice is overcome by using the same heatsink for bothdevices and the temperature feedback between the deviceswill keep the current sharing very constant because thelifetime of both devices will vary together and one will track theother constantly. Because the current tail is the same in aparalleled configuration as for a single device, the destruction

15MOTOROLA

of the device due to life time variation is the same as for singledevices used in a scaled down circuit. If the designer did notconsider the temperature effect of the current tail, VCE(on), andthe energy loss, the device may fail due to excessive energydissipated by the device at high temperature. However, in aparallel operation, unless a large quantity of the devices areparalleled for very high current levels, the failure of the devicein paralleled operation would be the same as in a single deviceoperation.

Threshold Voltage and Transconductance VariationThreshold voltage and transconductance are MOSFET

characteristics. Two devices with different MOSFET thresholdvoltages and transconductance were chosen, and theresultant waveform is shown in Figure 3. The turn–on delayoccurs for the higher threshold voltage device because ittakes longer for the gate voltage to charge up the gate–emittercapacitance to its threshold voltage. Not only does thethreshold voltage cause the delay, but the lowertransconductance will cause delay during the turn–onbecause the device resistance is higher than the other deviceuntil its gate voltage becomes large enough so that theon–state resistance of both devices are primarily determinedby the bipolar emitter–base voltages. The static portion of thewaveform shows a current imbalance, and the device with thehigher transconductance conducts more current because itson–resistance is lower than the other device. At turn–off, acurrent spike exists for the device with the largertransconductance and smaller threshold voltage. The turn–offcurrent spike in the higher transconductance device occursbecause the resistance of the lower transconductance devicebecomes larger sooner than for the high transconductancedevice, and the inductor current is transferred to the lowerresistance device. The turn–off current spike introduced byvariation in transconductance and threshold voltage can bedetrimental to the device if its SOA has been exceeded.

Figure 3. Paralleled Operation of IGBTs with Kpand Vth Varied

HIGH Kp/LOW VthVCE

IC1

IC2

LOW Kp/HIGH Vth

Temperature Dependency of Vth and Kp. With an increasein temperature, both of the parameters will be decreased. Fora high–gate voltage, the on–state voltage will tend to increasewith temperature, but because the IGBT has dual devicecharacteristics, the BJT emitter–base voltage decreases withtemperature due to the increase in intrinsic carrierconcentration. The decrease in BJT emitter–base voltage willnegate the decrease in transconductance, and as a result, the

amount of current seen by the device will be changed very littleor not at all. But if the current level is high enough, theMOSFET effect will dominate and the device VCE(sat) willincrease with temperature. This increase in on–resistance ofthe device will cause the other device to take more of thecurrent, and thereby always keep the current–sharing wellbalanced. Unless the parameters are significantly different,static current sharing is well balanced from device to device.

During turn–off, however, the device with highertransconductance will conduct most of the current becausethe MOSFET channel resistance dominates during switching.If the variation in transconductance is wide enough, one of thedevices can be destroyed due to excessive current spike.

Just as for the transconductance, the threshold voltage ofthe IGBT will decrease with the increase in temperature. Justas variation in transconductance will introduce turn–off currentspike, large variation in threshold voltage can cause dynamiccurrent imbalance because one device will turn off faster thanthe other device. During the static operation, the thresholdvoltage will have no effect. However, the decrease intransconductance counterbalances the effect of the decreasein threshold voltage, and the current spike is independent ofthe temperature.

USING COMMON HEATSINK

With common heatsink, the parameter variation in bothdevices will approximately be equal, and as a result, thedynamic turn–off current imbalance will not be improvedsignificantly if the designer did not pay attention to the Vth andKp. In fact, using a separate heatsink will actually improve thedynamic current sharing for the IGBTs. Static current sharingis greatly improved in IGBTs because the lifetimes of thedevices tend to increase proportionally to other devices withtemperature. Using a common heatsink will improve the staticcurrent sharing, but large dynamic instability can still beintroduced if Kp and Vth variation is not minimized.

EFFECT OF CIRCUIT LAYOUT

Just as in normal operation of the single device, the circuitlayout is very important in the parallel operation of the devices.Large variation in common–emitter inductance has beenshown to be the biggest contributor to the cause of dynamiccurrent imbalance of the devices. If one of the device’semitter–ground inductance is large while the other devicesees low inductance, a large current spike is observed by thelower inductance device because it turns on much faster thanthe other. It was discussed earlier that the large emitterinductance introduces large voltage drop and results inclamping of the gate current during the turn–on. So more of thegate current is diverted to the device with lowercommon–emitter inductance. With the interaction of parasiticcapacitors and nonlinear voltage–dependent junctioncapacitance of the devices, it will oscillate with largecommon–emitter inductance. This will be sensed by the otherdevice, and they will together oscillate out of phase with eachother.

EFFECT OF GATE RESISTANCE

If separate gate resistors are used for each device, it willintroduce a variation in delay time (or storage time). Thedevice with longer turn–off time will stay on longer, and thelower storage time device will transfer its current to the other

16 MOTOROLA

device. This will introduce more power dissipation in onedevice and introduce thermal instability if separate heat sinksare used.

If careful attention has been given to the circuit layout, andcommon–emitter inductance has been minimized, using asingle–gate resistor for both devices will reduce the turn–offstorage time variation because the device with higher storagetime will keep the other device conducting to a value which isdependent on the device transconductance.

SUMMARY

Many of the problems associated with paralleling of powerdevices can be greatly reduced by using IGBTs. It has beenshown that the device characteristics of the IGBT devicefavors parallel operation as opposed to BJTs. Its dual devicecharacteristics can be utilized to give design engineers verysatisfactory performance under static and dynamic currentsharing of the devices. Problems associated with parallelingIGBTs can be minimized and deterred if careful attention isgiven to parameter variations, careful circuit layout(minimizing parasitic inductance), and using commonheatsinks. Remember that using a common heatsink does notimprove the dynamic current imbalance if parametervariations of Kp and Vth are large. Static current sharing isincreased with the use of common heatsink. Most of the failureof the devices in paralleled operation can be contributed toneglect of device temperature effect and not derating the partsas they should have.

In summary, the following criteria should be met forparalleling IGBTs:

1. Minimize the spread of lifetime, Kp, and Vth between thedevices to be paralleled

2. Minimize the common–emitter inductance difference

3. Take all the precautions just as if the devices wereoperating as single devices

4. Use single gate resistors to drive the gates to reduce thestorage time variations

5. Use a common heatsink for all of the devices

6. Understand which characteristics will dominate the parallel operation (BJT or MOSFET)

7. Calculate the junction temperature using worst casenumbers

ACKNOWLEDGMENTS

The author wishes to thank the following people for theirinputs and many interesting discussions: Steve Robb, BillFragale, Scott Deuty, Kim Gauen, Rahul Chokhawala,Rodrigo Borras, and special thanks to A. R. Hefner for manylong and interesting telephone conversations which havebeen so valuable to the materials in this paper.

REFERENCES

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[1]

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Hefner, A. R. “Characterization and Modeling of thePower Insulated Gate Bipolar Transistor,” PhD.Dissertation (July 23, 1987), pp. 17–18.

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Baliga, B. J. “Temperature Behavior of InsulatedGate Transistor Characteristics.” Solid StateElectronics, Vol. 28, no. 3. (1985), pp. 289–297.

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[3]

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Letor, Romeo. “Static and Dynamic Behavior ofParalleled IGBT’s.” IEEE Trans. IndustryApplications, Vol. 28 (1992), pp. 395–402.

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Rinehart, Larry and Heron, Chuck. “ApplicationAdvantages Using IGBT Technology,” App Note,IXYS Corporation

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[5]

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Hefner, A. R. “A Dynamic Electro–Thermal Model forthe IGBT.” IEEE Trans., Vol. 30 (1994), pp. 394–405.ÁÁÁ

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Hefner, A. R. “An Improved Understanding for theTransient Operation of the Power Insulated GateBipolar Transistor (IGBT).” IEEE Power ElectronicsSpecialists Conf. (1989), pp. 303.

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Mitter, C. S., Hefner, A. R., Chen, D. Y., and Lee, F.C. “Insulated Gate Bipolar Transistor (IGBT)Modeling Using IG–Spice.” IEEE Trans. IndustryApplications, Vol. 30 (1993), pp. 24–33.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in differentapplications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure ofthe Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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AN1540/D

◊

1MOTOROLA

Prepared by: Jack Takesuye and Scott DeutyMotorola Inc.

INTRODUCTION

As power conversion relies more on switched applications,semiconductor manufacturers need to create products thatapproach the ideal switch. The ideal switch would have:1) zero resistance or forward voltage drop in the on–state,2) infinite resistance in the off–state, 3) switch with infinitespeed, and 4) would not require any input power to make itswitch.

When using existing solid–state switch technologies, thedesigner must deviate from the ideal switch and choose adevice that best suits the application with a minimal loss ofefficiency. The choice involves considerations such asvoltage, current, switching speed, drive circuitry, load, andtemperature effects. There are a variety of solid state switchtechnologies available to perform switching functions;however, all have strong and weak points.

HIGH VOLTAGE POWER MOSFETs

The primary characteristics that are most desirable in asolid–state switch are fast switching speed, simple driverequirements and low conduction loss. For low voltageapplications, power MOSFETs offer extremely lowon–resistance, RDS(on), and approach the desired idealswitch. In high voltage applications, MOSFETs exhibitincreased RDS(on) resulting in lower efficiency due toincreased conduction losses. In a power MOSFET, theon–resistance is proportional to the breakdown voltage raisedto approximately the 2.7 power (1).

MOSFET technology has advanced to a point where celldensities are limited by manufacturing equipment capabilitiesand geometries have been optimized to a point where theRDS(on) is near the predicted theoretical limit. Since the celldensity, geometry and the resistivity of the device structureplay a major role, no significant reduction in the RDS(on) isforeseen. New technologies are needed to circumvent theproblem of increased on–resistance without sacrificingswitching speed.

RDS(on) V2.7DSS (1)

ENTER THE IGBT

By combining the low conduction loss of a BJT with theswitching speed of a power MOSFET an optimal solid stateswitch would exist. The Insulated–Gate Bipolar Transistor(IGBT) technology offers a combination of these attributes.

The IGBT is, in fact, a spin–off from power MOSFETtechnology and the structure of an IGBT closely resemblesthat of a power MOSFET. The IGBT has high input impedanceand fast turn–on speed like a MOSFET. IGBTs exhibit anon–voltage and current density comparable to a bipolartransistor while switching much faster. IGBTs are replacingMOSFETs in high voltage applications where conductionlosses must be kept low. With zero current switching orresonant switching techniques, the IGBT can be operated inthe hundreds of kilohertz range [1].

Although turn–on speeds are very fast, turn–off of the IGBTis slower than a MOSFET. The IGBT exhibits a current fall timeor “tailing.” The tailing restricts the devices to operating atmoderate frequencies (less than 50 kHz) in traditional “squarewaveform” PWM, switching applications.

At operating frequencies between 1 and 50 kHz, IGBTs offeran attractive solution over the traditional bipolar transistors,MOSFETs and thyristors. Compared to thyristors, the IGBT isfaster, has better dv/dt immunity and, above all, has better gateturn–off capability. While some thyristors such as GTOs arecapable of being turned off at the gate, substantial reversegate current is required, whereas turning off an IGBT onlyrequires that the gate capacitance be discharged. A thyristorhas a slightly lower forward–on voltage and higher surgecapability than an IGBT.

MOSFETs are often used because of their simple gate driverequirements. Since the structure of both devices are sosimilar, the change to IGBTs can be made without having toredesign the gate drive circuit. IGBTs, like MOSFETs, aretransconductance devices and can remain fully on by keepingthe gate voltage above a certain threshold.

As shown in Figure 1a, using an IGBT in place of a powerMOSFET dramatically reduces the forward voltage drop atcurrent levels above 12 amps. By reducing the forward drop,the conduction loss of the device is decreased. The gradualrising slope of the MOSFET in Figure 1a can be attributed tothe relationship of VDS to RDS(on). The IGBT curve has anoffset due to an internal forward biased p–n junction and a fastrising slope typical of a minority carrier device.

It is possible to replace the MOSFET with an IGBT andimprove the efficiency and/or reduce the cost. As shown inFigure 1b, an IGBT has considerably less silicon area than asimilarly rated MOSFET. Device cost is related to silicon area;therefore, the reduced silicon area makes the IGBT the lowercost solution. Figure 1c shows the resulting package areareduction realized by using the IGBT. The IGBT is more spaceefficient than an equivalently rated MOSFET which makes itperfect for space conscious designs.

Order this documentby AN1541/D

SEMICONDUCTOR APPLICATION NOTE

Motorola, Inc. 1995

2 MOTOROLA

FORWARD DROP (VOLTS)

Figure 1a. Reduced Forward Voltage Drop ofIGBT Realized When Compared to a MOSFET

with Similar Ratings

40

35

30

25

20

15

10

5

01086420

PEAK

CU

RR

ENT

THR

OU

GH

DEV

ICE

(AM

PS)

VCE(sat)MGW20N60D IGBT

VDS MTW20N50EMOSFET

When compared to BJTs, IGBTs have similar ratings interms of voltage and current. However, the presence of anisolated gate in an IGBT makes it simpler to drive than a BJT.BJTs require that base current be continuously supplied in aquantity sufficient enough to maintain saturation. Basecurrents of one–tenth of the collector current are typical tokeep a BJT in saturation. BJT drive circuits must be sensitiveto variable load conditions. The base current of a BJT mustbe kept proportional to the collector current to preventdesaturation under high–current loads and excessive basedrive under low–load conditions. This additional base currentincreases the power dissipation of the drive circuit. BJTs areminority carrier devices and charge storage effects includingrecombination slow the performance when compared tomajority carrier devices such as MOSFETs. IGBTs alsoexperience recombination that accounts for the current“tailing” yet IGBTs have been observed to switch faster thanBJTs.

Thus far, the IGBT has demonstrated certain advantagesover power MOSFETs with the exception of switching speed.Since the initial introduction of IGBTs in the early 1980s,semiconductor manufacturers have learned how to make thedevices faster. As illustrated in Figure 2, some trade–offs inconduction loss versus switching speed exist. Lowerfrequency applications can tolerate slower switching devices.

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

Figure 1b. Reduced Die Size of IGBT Realized When Compared to a MOSFET with Similar Ratings

0.10

0.05

01

AREA

(SQ

. IN

CH

ES)

IGBT DIE SIZE(0.17 X 0.227)

MOSFET DIE SIZE(0.35 X 0.26)

ÇÇÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

Figure 1c. Reduced Package Size of IGBT RealizedWhen Compared to a MOSFET with Similar Ratings

0.60

0.20

01

AREA

(SQ

. IN

CH

ES)

IGBT PACKAGESIZE (TO–220)

MOSFET PACKAGESIZE (T0–247)

ÇÇÉ

0.40

Because the loss period is a small percentage of the total ontime, slower switching is traded for lower conduction loss. Ina higher frequency application, just the opposite would be trueand the device would be made faster and have greaterconduction losses. Notice that the curves in Figure 2 showreductions in both the forward drop (VCE(sat)) and the fall time,tf of newer generation devices. These capabilities make theIGBT the device of choice for applications such as motordrives, power supplies and inverters that require devices ratedfor 600 to 1200 volts.

Figure 2. Advanced Features Offered by the Latest Motorola IGBTTechnologies for Forward Voltage Drop (V CE(sat) ) and Fall Time (t f)

tf (µs)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

01.00.80.60.40.20 0.90.70.50.3

1ST GENERATION COMPETITOR 1985

2ND GENERATION COMPETITOR 1989

1ST GENERATION MOTOROLA 1993

3RD GENERATION COMPETITOR 1993

2ND GENERATION MOTOROLA DEMONSTRATED

V CE(

sat) (V

OLT

S)

HIGH SPEEDSERIES

LOW SATURATIONSERIES

0.1

3MOTOROLA

CHARACTERISTICS OF IGBTs: DEVICE STRUCTURE

The structure of an IGBT is similar to that of a doublediffused (DMOS) power MOSFET. One difference between aMOSFET and an IGBT is the substrate of the starting material.By varying the starting material and altering certain processsteps, an IGBT may be produced from a power MOSFETmask; however, at Motorola mask sets are designedspecifically for IGBTs. In a MOSFET the substrate is N+ asshown in Figure 3b. The substrate for an IGBT is P+ as shownin Figure 3a.

Figure 3a. Cross Section and Equivalent Schematicof an Insulated Gate Bipolar Transistor (IGBT) Cell

POLYSILICON GATE

N+

P+

N– EPI

N+ BUFFER

P+ SUBSTRATE

P–

Rmod

EMITTER

N+

P+

P–

COLLECTOR

GATE

NPNMOSFET

PNP

KEYMETALSiO2

Rshorting

Figure 3b. Cross Section and EquivalentSchematic of an Metal–Oxide–Semiconductor

Field–Effect Transistor (MOSFET) Cell

JFETchannel

Drain–to–Source Body Diode(Created when NPN

base–emitter is properlyshorted by source metal)

POLYSILICON GATE

N+

P+

N– EPI

N+ SUBSTRATE

SOURCE

N+

P+

DRAIN

NPN

KEYMETALSiO2

GATE

P–

The n– epi resistivity determines the breakdown voltage ofa MOSFET as mentioned earlier using relationship (1).

RDS(on) V2.7DSS (1)

To increase the breakdown voltage of the MOSFET, then– epi region thickness (vertical direction in figure) isincreased. As depicted in the classical resistance relationship(2), reducing the RDS(on) of a high voltage device requiresgreater silicon area A to make up for the increased n– epiregion.

R 1A

(2)

Device designers were challenged to overcome the effectsof the high resistive n– epi region. The solution to this came inthe form of conductivity modulation. The n– epi region to thiswas placed on the P+ substrate forming a p–n junction whereconductivity modulation takes place. Because of conductivitymodulation, the IGBT has a much greater current density thana power MOSFET and the forward voltage drop is reduced.Now the P+ substrate, n– epi layer and P+ “emitter” form a BJTtransistor and the n– epi acts as a wide base region.

The subject of current tailing has been mentioned severaltimes. Thus far, the device structure as shown in Figure 3provides insight as to what causes the tailing. Minority carriersbuild up to form the basis for conductivity modulation. Whenthe device turns off, these carriers do not have a current pathto exit the device. Recombination is the only way to eliminatethe stored charge resulting from the build–up of excesscarriers. Additional recombination centers are formed byplacing an N+ buffer layer between the n– epi and P+substrate.

While the N+ buffer layer may speed up the recombination,it also increases the forward drop of the device. Hence thetradeoff between switching speed and conduction lossbecomes a factor in optimizing device performance.Additional benefits of the N+ buffer layer include preventingthermal runaway and punch–through of the depletion region.This allows a thinner n– epi to be used which somewhatdecreases forward voltage drop.

Figure 4b. MOSFET Schematic Symbol

Figure 4a. IGBT Schematic Symbol

COLLECTOR

EMITTER

GATE

GATE

SOURCE

DRAIN

4 MOTOROLA

The IGBT has a four layer (P–N–P–N) structure. Thisstructure resembles that of a thyristor device known as aSilicon Controlled Rectifier (SCR). Unlike the SCR where thedevice latches and gate control is lost, an IGBT is designedso that it does not latch on. Full control of the device can bemaintained through the gate drive.

To maximize the performance of the IGBT, process stepsare optimized to control the geometry, doping and lifetime.The possibility of latching is also reduced by strategicprocessing of the device. Geometry and doping levels areoptimized to minimize the on–voltage, switching speed andachieve other key parametric variations. Because the IGBT isa four–layer structure, it does not have the inverse paralleldiode inherent to power MOSFETs. This is a disadvantage tomotor control designers who use the anti–parallel diode torecover energy from the motor.

Like a power MOSFET, the gate of the IGBT is electricallyisolated from the rest of the chip by a thin layer of silicondioxide, SiO2. The IGBT has a high input impedance due tothe isolated gate and it exhibits the accompanyingadvantages of modest gate drive requirements and excellentgate drive efficiency.

Equivalent Circuit of IGBTFigure 4b shows the terminals of the IGBT as determined by

JEDEC. Notice that the IGBT has a gate like a MOSFET yetit has an emitter and a collector like a BJT.

The operation of the IGBT is best understood by againreferring to the cross section of the device and its equivalentcircuit as shown in Figure 3a. Current flowing from collector toemitter must pass through a p–n junction formed by the P+substrate and n– epi layer. This drop is similar to that seen ina forward biased p–n junction diode and results in an offsetvoltage in the output characteristic. Current flow contributionsare shown in Figure 3a using varying line thickness with thethicker lines indicating a high current path. For a fast device,the N+ buffer layer is highly doped for recombination andspeedy turn off. The additional doping keeps the gain of thePNP low and allows two–thirds of the current to flow throughthe base of the PNP (electron current) while one–third passesthrough the collector (hole current).

Rshorting is the parasitic resistance of the P+ emitter region.Current flowing through Rshorting can result in a voltageacross the base–emitter junction of the NPN. If thebase–emitter voltage is above a certain threshold level, theNPN will begin to conduct causing the NPN and PNP toenhance each other’s current flow and both devices canbecome saturated. This results in the device latching in afashion similar to an SCR. Device processing directs currentswithin the device and keeps the voltage across Rshorting low toavoid latching. The IGBT can be gated off unlike the SCRwhich has to wait for the current to cease allowingrecombination to take place in order to turn off. IGBTs offer anadvantage over the SCR by controlling the current with thedevice, not the device with the current. The internal MOSFETof the IGBT when gated off will stop current flow and at thatpoint, the stored charges can only be dissipated throughrecombination.

The IGBT’s on–voltage is represented by sum of the offsetvoltage of the collector to base junction of the PNP transistor,the voltage drop across the modulated resistance Rmod andthe channel resistance of the internal MOSFET. Unlike theMOSFET where increased temperature results in increasedRDS(on) and increased forward voltage drop, the forwarddrop of an IGBT stays relatively unchanged at increasedtemperatures.

Switching SpeedUntil recently, the feature that limited the IGBT from

serving a wide variety of applications was its relatively slowturn–off speed when compared to a power MOSFET. Whileturn–on is fairly rapid, initial IGBTs had current fall times ofaround three microseconds.

The turn–off time of an IGBT is slow because many minoritycarriers are stored in the n– epi region. When the gate isinitially brought below the threshold voltage, the n– epicontains a very large concentration of electrons and there willbe significant injection into the P+ substrate and acorresponding hole injection into the n– epi. As the electronconcentration in the n–region decreases, the electroninjection decreases, leaving the rest of the electrons torecombine. Therefore, the turn–off of an IGBT has twophases: an injection phase where the collector current fallsvery quickly, and a recombination phase in which the collectorcurrent decrease more slowly. Figure 5 shows the switchingwaveform and the tail time contributing factors of a “fast” IGBTdesigned for PWM motor control service.

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÇÇÇÇÇÇÇÇÇÇÇÇ

Figure 5. IGBT Current Turn–off Waveform

6

5

4

3

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1

0

–110008006004002000

I C (A

MPS

)

TAIL TIME of MOTOROLA GEN. 2 IGBT #2 in1.0 hp MOTOR DRIVE at 1750 RPM

PNP TURN–OFFPORTION

TAIL TIME

MOSFET TURN–OFFPORTION

In power MOSFETs, the switching speed can be greatlyaffected by the impedance in the gate drive circuit. Efforts tominimize gate drive impedance for IGBTs are alsorecommended. Also, choose an optimal device based onswitching speed or use a slower device with lower forwarddrop and employ external circuitry to enhance turn off. Aturn–off mechanism is suggested in a paper by Baliga et al [2].

5MOTOROLA

A FINAL COMPARISON OF IGBTs, BJTs ANDPOWER MOSFETs

The conduction losses of BJTs and IGBTs is related to theforward voltage drop of the device while MOSFETs determineconduction loss based on RDS(on). To get a relativecomparison of turn–off time and conduction associatedlosses, data is presented in Table 1 where the on–resistancesof a power MOSFET, an IGBT and a BJT at junctiontemperatures of 25°C and 150°C are shown.

Note that the devices in Table 1 have approximately thesame ratings. However, to achieve these ratings the chip sizeof the devices vary significantly. The bipolar transistor requires1.2 times more silicon area than the IGBT and the MOSFETrequires 2.2 times the area of the IGBT to achieve the sameratings. This differences in die area directly impacts the costof the product. At higher currents and at elevatedtemperatures, the IGBT offers low forward drop and aswitching time similar to the BJT without the drive difficulties.Table 1 confirms the findings offered earlier in Figure 1a andelaborates further to include a BJT comparison andtemperature effects. The reduced power conduction lossesoffered by the IGBT lower power dissipation and heat sinksize.

Thermal ResistanceAn IGBT and power MOSFET produced from the same size

die have similar junction–to–case thermal resistance becauseof their similar structures. The thermal resistance of a powerMOSFET can be determined by testing for variations intemperature sensitive parameters (TSPs). These parametersare the source–to–drain diode on–voltage, thegate–to–source threshold voltage, and the drain–to–sourceon–resistance. All previous measurements of thermalresistance of power MOSFETs at Motorola were performedusing the source–to–drain diode as the TSP. Since an IGBTdoes not have an inverse parallel diode, another TSP had tobe used to determine the thermal resistance. Thegate–to–emitter threshold voltage was used as the TSP tomeasure the junction temperature of an IGBT to determine itsthermal resistance. However before testing IGBTs, acorrelation between the two test methods was established bycomparing the test results of MOSFETs using both TSPs. Bytesting for variations in threshold voltage, it was determinedthat the thermal resistance of MOSFETs and IGBTs areessentially the same for devices with equivalent die size .

Short Circuit Rated DevicesUsing IGBTs in motor control environments requires the

device to withstand short circuit current for a given period.Although this period varies with the application, a typicalvalue of ten microseconds is used for designing thesespecialized IGBT’s. Notice that this is only a typical value andit is suggested that the reader confirm the value given on thedata sheet. IGBTs can be made to withstand short circuitconditions by altering the device structure to include anadditional resistance (Re, in Figure 6) in the main current path.The benefits associated with the additional series resistanceare twofold.

Figure 6. Cross Section and Equivalent Schematicof a Short Circuit Rated Insulated Gate

Bipolar Transistor Cell

POLYSILICON GATE

N+

P+

N– EPI

N+ BUFFER

P+ SUBSTRATE

P–

Rmod

EMITTER

N+

P+

P–

COLLECTOR

GATE

NPNMOSFET

PNP

KEYMETALSiO2

Rshorting

Re

First, the voltage created across Re, by the large currentpassing through Re, increases the percentage of the gatevoltage across Re, by the classic voltage divider equation.Assuming the drive voltage applied to the gate–to–emitterremains the same, the voltage actually applied across thegate–to–source portion of the device is now lower, and thedevice is operating in an area of the transconductance curvethat reduces the gain and it will pass less current.

Table 1. Advantages Offered by the IGBT When Comparing the MOSFET, IGBT and Bipolar Transistor On–Resistances(Over Junction Temperature) and Fall Times (Resistance Values at 10 Amps of Current)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CharacteristicÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TMOSÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IGBTÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BipolarÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁCurrent Rating

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ20 A

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ20 A

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ20 AÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVoltage RatingÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ500 V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ600 V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ500 V*ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

R(on) @ TJ = 25°CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.2 ΩÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.24 ΩÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.18 ΩÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

R(on) @ TJ = 150°CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.6 ΩÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.23 ΩÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

0.24 Ω**

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Fall Time (Typical) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

40 ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

200 ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

200 ns

* Indicates VCEO Rating** BJT TJ = 100°C

6 MOTOROLA

Second, the voltage developed across Re results in asimilar division of voltage across Rshorting and VBE of theNPN transistor. The NPN will be less likely to attain a VBEhigh enough to turn the device on and cause a latch–upsituation.

The two situations described work together to protect thedevice from catastrophic failure. The protection period isspecified with the device ratings, allowing circuit designersthe time needed to detect a fault and shut off the device.

The introduction of the series resistance Re also results inadditional power loss in the device by slightly elevating theforward drop of the device. However, the magnitude of shortcircuit current is large enough to require a very low Re value.The additional conduction loss of the device due to thepresence of Re is not excessive when comparing a shortcircuit rated IGBT to a non–short circuit rated device.

Anti–Parallel DiodeWhen using IGBT’s for motor control, designers have to

place a diode in anti–parallel across the device in order tohandle the regenerative or inductive currents of the motor. Asdiscussed earlier, due to structural differences the IGBT doesnot have a parasitic diode like that found in a MOSFET.Designers found that the diode within the MOSFET was, infact, a parasitic, i.e., not optimized in the design process, andits performance was poor for use as a current recovery devicedue to slow switching speed. To overcome the lack ofperformance, an optimized anti–parallel diode was usedacross the MOSFET source–to–drain. Placing a packageddiode external to the MOSFET itself created performanceproblems due to the switching delays resulting from theparasitics introduced by the packages. The optimal setup is tohave the diode copackaged with the device. A specific line ofIGBTs has been created by Motorola to address this issue.These devices work very well in applications where energy isrecovered to the source and are favored by motor controldesigners.

Like the switching device itself, the anti–parallel diodeshould exhibit low leakage current, low forward voltage dropand fast switching speed. As shown in Figure 7, the diodeforward drop multiplied by the average current it passes is thetotal conduction loss produced. In addition, large reverserecovery currents can escalate switching losses. A detailedexplanation of reverse recovery can be found in theAppendix. A secondary effect caused by large reverserecovery currents is generated EMI at both the switchingfrequency and the frequency of the resulting ringingwaveform. This EMI requires additional filtering to bedesigned into the circuit. By copackaging parts, the parasiticinductances that contribute to the ringing are greatly reduced.Also, copackaged products can be used in designs to reducepower dissipation and increase design efficiency.

Figure 7. Waveforms Associated with Anti–Parallel Diode Turn–off

IRM(rec)

TIME

TIME

TIME

POWER

VOLTAGE

CURRENT

IIGBT

IDIODE

Vf

APPLICATION OF IGBTs: PULSE WIDTH MODULATED INDUCTION

MOTOR DRIVE APPLICATION

Line–operated, pulse–width modulated, variable–speedmotor drives are an application well suited for IGBTs. In thisapplication, as shown in Figure 8, IGBTs are used as thepower switch to PWM the voltage supplied to a motor tocontrol its speed.

Depending on the application, the IGBT may be required tooperate from a full–wave rectified line. This can requiredevices to have six hundred volt ratings for 230 VAC linevoltage inputs, and twelve hundred volt ratings for 575 VACvolt line inputs. IGBTs that block high voltage offer fastswitching and low conduction losses, and allow for the designof efficient, high frequency drives of this type. Devices used inmotor drive applications must be robust and capable ofwithstanding faults long enough for a protection scheme to beactivated. Short circuit rated devices offer safe, reliable motordrive operation.

CONCLUSION

The IGBT is a one of several options for designers to choosefrom for power control in switching applications. The featuresof the IGBT such as high voltage capability, low on–resistance,ease of drive and relatively fast switching speeds makes it atechnology of choice for moderate speed, high voltageapplications. New generations of devices will reduce theon–resistance, increase speed and include levels ofintegration that simplify protection schemes and device driverequirements. The reliability and performance advantages ofIGBTs are value added traits that offer circuit designers energyefficient options at reduced costs.

7MOTOROLA

IGBT 1/2 BRIDGEIGBT

1/2 BRIDGE

Figure 8. Typical Pulse–Width, Modulated, Variable–Speed Induction Motor Drives Are Where IGBT’s Offer Performance Advantages

230 VAC

TEMPERATURECONTROL SYSTEM

I/OLON

CONTROL IC MCUOR ASIC

MIXED MODE ICCUSTOM LINEAR

OR STANDARD CELL

GATE DRIVE HVICOR

OPTO & LVIC

DIODE BRIDGE

FILTER CAPACITOR

INDUCTION MOTOR

IGBT 1/2 BRIDGE

PHASE CURRENTS AND VOLTAGES

ACKNOWLEDGEMENTS

The writing of this document was assisted by a number ofinternal device designers. Their assistance was greatlyappreciated by the authors. Bill Fragale, Steve Robb andVasudev Venkatesan provided device operation insight andreference materials. Graphic material was provided by BasamAlmesfer and Steve Robb. Finally, C. S. Mitter assisted withediting and accuracy of the material.

REFERENCES

[1] D. Y. Chen, J. Yang, and J. Lee “Application of theIGT/COMFET to Zero–Current Switching ResonantConverters,” PESC, 1987.[2] B. J. Baliga, “Analysis of Insulated Gate Transistor Turn–offCharacteristics,” IEEE Electron Device Lett. EDL–6, (1985),pp. 74–77 .[3] B. J. Baliga, “Switching Speed Enhancement in InsulatedGate Transistors by Electron Irradiation,” IEEE Transactionson Electron Devices, ED–31, (1984), pp. 1790–1795.

8 MOTOROLA

APPENDIX

Diode Reverse Recovery Analysis [4]

Figure A–1. Reverse Recovery Waveform

total reverse recovery timefall time due to stored minority chargeapplication and device dependentpeak reverse recovery current

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

tb

ta

trr

IRM(rec)

IF

di/dt

Qa Qb

trr =ta =tb =IRM(rec) =

A typical reverse recovery waveform is shown inFigure A–1. The reverse recovery time trr has beentraditionally defined as the time from diode currentzero–crossing to where the current returns to within 10% of thepeak recovery current IRM(rec). This does not give enoughinformation to fully characterize the waveform shape. A betterway to characterize the rectifier reverse recovery is to partitionthe reverse recovery time into two different regions, ta and tb,as shown in Figure A–1. The ta time is a function of the forwardcurrent and the applied di/dt. A charge can be assigned to thisregion denoted Qa, the area under the curve. The tb portion ofthe reverse recovery current is not very well understood.Measured tb times vary greatly with the switch characteristic,circuit parasitics, load inductance and the applied reversevoltage. A relative softness can be defined as the ratio of tb tota. General purpose rectifiers are very soft (softness factor ofabout 1.0), fast recovery diodes are fairly soft (softness factorof about 0.5) and ultrafast rectifiers are very abrupt (softnessfactor of about 0.2).

[4] Source: “Motor Controls,” TMOS Power MOSFETTransistor Data, Q4/92, DL135, Rev 4, (Phoenix: Motorola,Inc., 1992), pp. 2–9–22 to 2–9–23.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in differentapplications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure ofthe Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:USA / EUROPE: Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

AN1541/D

◊

AN-983 (v.Int)

IGBT Characteristics(HEXFET® is a trademark of International Rectifier)

Topics covered:

How the IGBT complements the MOSFETSilicon structure and equivalent circuitConduction characteristics and “switchback”Switching characteristicsLatchingSafe Operating AreaTransconductanceHow to read the data sheetFamilies of IGBTs

1. HOW THE IGBT COMPLEMENTS THE POWER MOSFET

Switching speed, peak current capability, ease of drive, wide SOA, avalanche and dv/dt capability have made power MOSFETsthe logical choice in new power electronic designs. These advantages, a natural consequence of being majority carrier devices,are partly mitigated by their conduction characteristics which are strongly dependent on temperature and voltage rating.

Furthermore, as the voltage rating goes up, the inherent reverse diode displays increasing Qrr and Trr which leads to increasingswitching losses.

IGBTs on the other hand, being minority carrier devices, have superior conduction characteristics, while sharing many of theappealing features of power MOSFETs such as ease of drive, wide SOA, peak current capability and ruggedness. Generallyspeaking, the switching speed of an IGBT is inferior to that of power MOSFETs. However, as detailed in INT-990 Sec VIII, anew line of IGBTs from International Rectifier has switching characteristics that are very close to those of power MOSFETs,without sacrificing the much superior conduction characteristics.

The absence of the integral reverse diode gives the user the flexibility of choosing an external fast recovery diode to match aspecific requirement or to purchase a “co-pak”, i.e. an IGBT and a diode in the same package. The lack of an integral diode canbe an advantage or a disadvantage, depending on the frequency of operation, cost of diodes, current requirement, etc.

N+N+ P-

P+rb rb

GATE POLYSILICON OXIDE

N- EPI

EMITTER

N+ BUFFER LAYER

P+ SUBSTRATE

COLLECTOR

(a) DEVICE STRUCTURE

C

E

G

(b) Device Symbol

rb

COLLECTOR

EMITTER

(c) EQUIVALENT CIRCUIT

Figure 1. Silicon cross-section of an IGBT with its equivalent circuit and symbol (N-Channel,enhancement mode). The terminal called collector is, actually, the emitter of the PNP. In spite of itssimilarity to the cross-section of a power MOSFET, operation of the two transistors is fundamentallydifferent, the IGBT being a minority carrier device.

AN-983 (v.Int)

2. SILICON STRUCTURE AND EQUIVALENT CIRCUIT

Except for the P+ substrate, the silicon cross-section of an IGBT (Figure 1) is virtually identical to that of a power MOSFET.Both devices share a similar polysilicon gate structure and P wells with N+ source contacts. In both devices the N- type materialunder the P wells is sized in thickness and resistivity to sustain the full voltage rating of the device.

However, in spite of the many similarities, the physical operation of the IGBT is closer to that of a bipolar transistor than to thatof a power MOSFET. This is due to the P+ substrate which is responsible for the minority carrier injection into the N-region andthe resulting conductivity modulation. In a power MOSFET, which does not benefit from conductivity modulation, a significantshare of the conduction losses occur in the N-region, typically 70% in a 500V device.

As shown in the equivalent circuit of Figure 1, the IGBT consists of a PNP driven by an N-Channel MOSFET in a pseudo-Darlington configuration. The JFET has been included in the equivalent circuit to represent the contriction in the flow of currentbetween adjacent P-wells. The cell density of the MOSFET structure is higher than that of a high-voltage, comparable technologyMOSFET and, consequently, has better Resistance-Area product.

The base region of the PNP is not brought out and the emitter-base PN junction, spanning the entire extension of the wafercannot be terminated nor passivated. This influences the turn-off and reverse blocking behavior of the IGBT, as will be explainedlater. The breakdown voltage of this junction is about 20V and is shown in the IGBT symbol as an unconnected terminal (Figure1).

3. CONDUCTION CHARACTERISTICS

As it is apparent from the equivalent circuit, the voltage drop across the IGBT is the sum of two components: a diode drop acrossthe P-N junction and the voltage drop across the driving MOSFET. Thus, unlike the power MOSFET, the on-state voltage dropacross an IGBT never goes below a diode threshold. The voltage drop across the driving MOSFET, on the other hand, has onecharacteristic that is typical of all low voltage MOSFETs: it is sensitive to gate drive voltage. This is apparent from Figures 12and 13 where, for currents that are close to their rated value, an increase in gate voltage causes a reduction in collector-to-emittervoltage. This is due to the fact that, within its operating range, the gain of the PNP increases with current and an increase in gatevoltage causes an increase in channel current, hence a reduction in voltage drop across the PNP. This is quite different from thebehavior of a high voltage power MOSFET that is largely insensitive to gate voltage.

As the final stage of a pseudo-Darlington, the PNP is never in heavy saturation and its voltage drop is higher than what could beobtained from the same PNP in heavy saturation. It should be noted, however, that the emitter of an IGBT covers the entire areaof the die, hence its injection efficiency and conduction drop are much superior to that of a bipolar transistor of the same size.

Two options are available to the device designer to decrease the conduction drop:

1. Reduce the on-resistance of the MOSFET. This can be done by increasing the die size and/or the cell density. 2. Increase the gain of the PNP. As explained later, this option is limited by latch-up considerations and voltage

withstanding capability.

International Rectifier has been pursuing the optimization of the MOSFET component of the IGBT to the point where its devicescan be correctly referred to as a "conductivity modulated MOSFET" with its characteristic features of high speed, low voltagedrop and efficient silicon utilization. Other semiconductor companies, on the other hand, have concentrated on the optimizationof the bipolar part and the resulting product should be more correctly referred to as a "MOSFET-driven transistor" with adifferent set of characteristics.

The dramatic impact of conductivity modulation on voltage drop can be seen from Figure 2 which compares a HEXFET® powerMOSFET and an IGBT of the same die size. Temperature dependence, very significant in a power MOSFET, is minimal in anIGBT, just enough to ensure current sharing of paralleled devices at high current levels under steady state conditions, as shownin Figure 14 for the IRGBC20U. This same figure shows that the temperature dependence of the voltage drops is different atdifferent current levels. This is because the diode component of this drop has a temperature coefficient that is initially negativebecoming positive at higher current levels. The MOSFET component, on the other hand, is positive. The problem is made morecomplex by the fact that these two components are weighted differently at different current and temperatures.

AN-983 (v.Int)

In addition to reducing the voltage drop and its temperaturecoefficient, conductivity modulation virtually eliminates itsdependence on the voltage rating. This is shown in Table I,where the conduction drops of four IGBTs of different voltageratings are compared with those of HEXFET®s at the samecurrent density. A common misconception is that powerMOSFETs exhibit a voltage dependence of the RDS(on) of thefollowing type:

R = RO Vα with α = 2.5,

i.e., the on-resistance increases with the voltage rating at ahigher rate than a square law. In reality, assuming that apower law is a true representation of the underlying physicalphenomena, the correct value would be ≈ 1.6, as can be easilyverified from the data sheets of any manufacturer. These datasheets will also contradict the common misconception thatpower MOSFETs have better silicon utilization at low voltage.In actual fact they achieve their highest power handlingcapability per unit area between 400V and 600V, even if theyare unbeatable at low voltages, on account of their resistivevoltage drop. The voltage drop of a conductivity modulateddevice with minority lifetime killing may exhibit a peculiarbehavior frequently referred to as ‘switchback’: the voltagedrop at low current and low temperature is higher thanexpected, suddenly dropping to its expected value if current ortemperature are increased. The term comes from the fact that,when measuring voltage drop with a curve tracer, the tracesuddenly ‘switches’ to the left of the screen as the currentincreases. This behavior is ascribed to lifetime killing which,in so far as it facilitates recombination, delays the onset ofconductivity modulation. Hence, the voltage drop for currentlevels below conductivity modulation is higher than for asomewhat higher collector current, after conductivitymodulation is established. This phenomenon is one of the causes of the “forward recovery” of fast (reverse recovery) diodes andof higher values of latching current in minority lifetime killed thyristors. A trace of this phenomenon can be seen in the “bump”in the VCE(Sat) portion of Figure 12. Notice that the bump disappears in Figure 13 because temperature increases the lifetime ofthe charges and speeds up the onset of conductivity modulation. Notice, also, that only the Ultrafast IGBTs exhibit thisphenomenon, because of higher levels of lifetime killing.

Rated Voltage IGBT 100 300 600 1200HEXFET® 100 250 500 1000

Typical Voltage Drop IGBT 1.5 2.1 2.4 3.1

@ 1.7A/mm2, 1000C HEXFET® 2.0 11.2 26.7 100

Table 1: Dependence of Voltage Drop From Voltage Rating

The voltage rating of the HEXFET® power MOSFETs used in this comparison are lower than the IGBTs to take into accounttheir avalanche capability.

4. SWITCHING CHARACTERISTICS

The biggest limitation to the turn-off speed of an IGBT is the lifetime of the minority carriers in the N- epi, i.e., the base of thePNP. Since this base is not accessible, external drive circuitry cannot be used to improve the switching time. It should beremembered, though, that since the PNP is in a pseudo-Darlington connection, it has no storage time and its turn-off time ismuch faster than the same PNP in heavy saturation. Even so, it may still be inadequate for many high frequency applications.

10A

IRF840

IRGBC40U

IRGBC40S

50

40

30

20

10

7

5

3

2

120 30 50 70 90 110 130 150

ON

-ST

AT

E V

OLT

AG

E D

RO

P (

VO

LTS

)JUNCTION TEMPERATURE (0C)

Figure 2. On-state voltage drop as temperature oftwo IGBTs of different switching characteristicscompared to those of a HEXFET of the same diesize (IRGBC40S and IRGBC40U vs IRF840).Conductivity modulation causes a dramaticimprovement in the on-state voltage drop. To takethe avalanche capability of the HEXFET intoaccount, a 500V device is compared with 600VIGBTs.

AN-983 (v.Int)

The charges stored in the base cause the characteristic “tail” inthe current waveform of an IGBT at turn-off (Figure 3). As theMOSFET channel stops conducting, electron current ceases andthe IGBT current drops rapidly to the level of the holerecombination current at the inception of the tail.

This tail increases turn-off losses and requires an increase in thedeadtime between the conduction of two devices in a half-bridge. Traditional lifetime killing techniques and/or an N+buffer layer to collect the minority charges at turn-off arecommonly used to speed-up recombination time.

Insofar as they reduce the gain of the PNP, these techniquesincrease the voltage drop. Pushed to the extreme, minoritylifetime killing causes a quasi-saturation condition at turn-on, asshown in Figure 4, where the turn-on losses have become largerthan the turn-off losses.

Thus, the gain of the PNP is constrained by conduction andturn-on losses on one hand, and by latching considerations onthe other, as explained in the next section. Like all minoritycarrier devices, the switching performance of an IGBT degradeswith temperature.

IGBTs operated in zero current switching may exhibit quasi-saturation losses at turn-on that are somewhat higher than inswitchmode circuits.

The low di/dt that is characteristic of this mode of operationemphasizes the "switchback" phenomenon described in the previoussection. Similarly, with zero-voltage turn-off, the IGBT mayexperience a short burst of current if the complementary device isturned on soon after the current has ceased in the one that wasconducting.

This is due to the fact that the turn-on of the complementary devicecauses the supply voltage to appear across the first IGBT, therebydepleting its base region and causing a final sweep-out of theminority carriers that were still left there. There is, however, acomponent of current that is due to the charging of the devicecapacitances and is totally unrelated to minority carriers.

5. LATCHING

As shown in the cross-section of Figure 1, the IGBT is made of four alternate P-N-P-N layers. Given the necessary conditions(αNPN + αPNP > 1) the IGBT could latch-up like a thyristor. The N+ buffer layer and the wide epi base reduce the gain of thePNP, while the gain of the NPN, which is the parasitic bipolar of the MOSFET, can be reduced with the same techniques [1] thatare commonly employed to give HEXFET®s their avalanche and dv/dt capability, mainly a drastic reduction of the r’b. If this r’bis not adequately reduced, "dynamic latching" could occur at turn-off when a high density of hole current flows in r’b, taking thegain of the parasitic NPN to much higher values.

6. SAFE OPERATING AREA

The safe operating area (SOA) describes the capability of a transistor to withstand significant levels of voltage and current at thesame time. The three main conditions that would subject an IGBT to this combined stress are the following:

VCE

IC

VCE : 100V/div.

IC : 5A/div., 0.2 µµs/div.

Figure 3. Turn-off waveform of a commercial IGBT at 250C,rated current. Notice the clean break at the inception of the"tail". Switching circuit as in Figure 16.

VCE

IC

ENERGYVCE: 100V/div.

IC: 10A/div.

E: 5 mJ/div., 1µµs/div.

Figure 4. Switching waveforms of a commerciallyavailable IGBT with heavy lifetime killing. It takesapproximately 0.5ms for the voltage to drop the last50V. The energy plot shows that the losses at turn-onare twice as high as those at turn-off. Switching circuitas in Figure 16.

AN-983 (v.Int)

1. Operation in short circuit. The current in the IGBT is limited by its gate voltage and transconductance and can reach valueswell in excess of 10 times its continuous rating. The level of hole current that flows underneath the N+ source contact cancause a drop across r’b, large enough to turn on the NPN parasitic bipolar with possible latching. This is normally prevented

by a reduction in r’b, as mentioned in the previous section or by a reduction of the total device transconductance. Since thissecond technique increases conduction losses and reduces switching speed, two families of IGBTs have been made availableby IR, one optimized for low conduction losses, the other for short circuit operation, as indicated in Section 9.

2. Inductive turn-off, sometimes referred to as "clamped IL." In an inductive turn-off the voltage swings from a few volts to the

supply voltage with constant current and with no channel current. These conditions are different from those described in theprevious section in so far as the load current is totally made up of holes flowing through r’b. For this reason somemanufacturers suggest the use of gate drive resistors to slow down the turn-off dv/dt and maintain some level of electroncurrent, thereby avoiding a potential "dynamic latching" condition. IGBTs from International Rectifier can be operated attheir maximum switching speed without any problem. Reasons to limit the switching speed should be external to the device(e.g., overshoots due to stray inductance), rather than internal.

3. Operation as a linear amplifier. Linear operation exercises the SOA of the IGBT in a combination of the two modes

described above. No detailed characterization of IGBTs as linear amplifiers has been carried out by IR, given the limited useof IGBTs in this type of application.

7. TRANSCONDUCTANCE

The current handling capability of a semiconductor canbe limited by thermal constraints or by gain /transconductance constraints. While the "headlinecurrent rating" of power semiconductors is based solelyon thermal considerations, it is entirely possible, as isfrequently the case with bipolar transistors, that thedevice cannot operate at the current level it isthermally capable of, because its gain has fallen to verylow values. As shown in Figure 5, thetransconductance of an IGBT tops out at current levelsthat are well beyond its thermal capability, while thegain of a bipolar of similar die size is on a steepdownslope within its current operating range. Theflattening out of transconductance occurs when thesaturation effects in the MOSFET channel, that reducethe base current of the PNP, combine with theflattening of the gain of the PNP. Since temperaturereduces the MOSFET channel current more than itincreases the gain of the PNP, the saturation intransconductance occurs at lower current as thetemperature increases.

Since lifetime killing reduces the gain of the PNP, the transconductance of fast IGBTs peaks at a lower level than those withoutlifetime killing. This, however, is a second order effect because the gain of the PNP is determined mainly by the N+ bufferlayer. The decrease in transconductance at very high current and its additional decrease with temperature helps protect the IGBTunder short circuit conditions. With a gate voltage of 15V, the current density of a standard IGBT from International Rectifierreaches values of 10-20A/mm2 in short circuit. This high transconductance is partly responsible for their superior switchingand conduction characteristics.

8. HOW TO READ THE DATA SHEET

International Rectifier prides itself on having one of the most comprehensive IGBT data sheets in the industry, with all theinformation required to operate the IGBT reliably. However, like all technical documents it requires a good understanding by theuser of the different terms and conditions. These are briefly explained in the following sections.

IRF450

IRGPC50UBUX98

1000C

1A 10A 100A 1000A1

2

4

710

20

40

70

100

gfe

hfe

COLLECTOR/DRAIN CURRENT

Figure 5. Current dependence of the transconductanceof an IGBT compared to that of a HEXFET and to thegain of a bipolar of approximately the same die size.The IGBT, like te power MOSFET, is not "gain limited."

AN-983 (v.Int)

8.1. The Headline Information

In addition to the mechanical layout, the front page gives the voltage drop at the 100ºC current ratings. The part number itselfcontains in coded form the key features of the IGBT, as explained in Figure 6.

8.2. The Absolute Maximum Ratings

This table sets up a number of constraints on device operation that apply under any circumstance.

Continuous Collector Current @ TC = 25°C and 100°C (IC). This represents the dc current level that will take the junction toits rated temperature from the stipulated case temperature. It is calculated with the following formula:

IT

V IC

j c CE on C

=•−

∆

θ ( ) @

where ∆Τ is the temperature rise from the stipulated case temperature to the maximum junction temperature (150°C) . Noticethat VCE(On) @ IC is not known because IC is not known. 1t can be found with few iterations .

It is clear, from this formula, that a current rating has no meaning without a corresponding junction and case temperature.Since in normal applications the case temperature is much higher than 25°C, the associated rating is of no practical value and isonly reported because transistors have been traditionally rated in this way. Figure 7 shows how this rating changes with casetemperature, with a junction temperature of 150°C, for a specific device.

Pulsed Collector Current (I CM). Within its thermal limits, the IGBT can be used to a peak current well above the ratedcontinuous DC current. The temperature rise during a high current transient can be calculated as indicated in Section Y. Thetest circuit is shown in Figure 8.

Collector-to-Emitter Voltage (V CE). Voltage across the IGBT should never exceed this rating, to prevent breakdown of thecollector-emitter junction. The breakdown itself is guaranteed in the Table of Electrical Characteristics .

IR G P C 4 0 U D2

INTERNATIONAL RECTIFIER

IGBT

PACKAGE DESIGNATOR

VOLTAGE DESIGNATOR

DIE SIZE

CO-PAK

SPEED DESIGNATOR

B TO-220P TO-247

D2 DIODE IS ONE DIE SIZE SMALLER

D1 DIODE IS TWO DIE SIZES SMALLER

S STANDARDF FASTM FAST, SHORT CIRCUITU ULTRAFASTK ULTRAFAST, SHORT CIRCUIT

MODIFIERC 600VE 800VF 900VG 1000VH 1200V

Figure 6. Simplified nomenclature code for commercial IGBTs from International Rectifier

AN-983 (v.Int)

Maximum Gate-to-Emitter Voltage (V GE). The gate voltageis limited by the thickness and characteristics of the gate oxidelayer. Though the gate dielectric rupture is typically around 80volts, the user is limited to 20V to limit current under faultconditions and to ensure long term reliability.

Clamped Inductive Load Current (I LM). This ratingguarantees that the device is able to repetitively turn off thespecified current with a clamped inductive load, as encounteredin most applications. In fact, the test circuit (Figure 9) exposesthe IGBT to the peak recovery current of the free-wheelingdiode, which adds a significant component to the turn-on losses(Figure 10). This rating guarantees a square switching SOA,i.e., that the device can sustain high voltage and high currentsimultaneously. The ILM rating is specified at 150°C, 80% of therated voltage. This complements the information supplied by theRBSOA.

Reverse Avalanche Energy (E ARV). This subject is coveredin detail in the BVECS section of the electrical characteristics .Maximum Power Dissipation @ 25°C and 100°C (PD). It iscalculated with the following formula:

PT

Dj c

=−

∆

θ

The same comments that were made on the Continuous Collector Current apply to Power Dissipation.Junction Temperature (Tj): the device can be operated in the industry standard range of -55°C to 150°C.

8.3. Thermal Resistance

Rthjc, Rthcs, Rthja are needed for the thermal design, as explained in INT-949

8.4. Electrical Characteristics

The purpose of this section is to provide a detailed characterization of the device so that the designer can predict with accuracyits behavior in a specific application.

Collector-to-Emitter Breakdown Voltage (BV CES). This parameter guarantees the lower limit of the distribution inbreakdown voltage. Breakdown is defined in terms of a specific leakage current and has a positive temperature coefficient (listedin the table as BVCES/∆T) of about 0.63V/°C. This implies that a device with 600V breakdown at 25°C would have a breakdownvoltage of 550V at -55°C.

1501251007550250

3

6

9

12

15

Tc, CASE TEMPERATURE ( 0C)

MA

XIM

UM

CO

LLE

CT

OR

CU

RR

EN

T (

AM

PS

DC

)

Figure 7. Maximum Collector Current vs. CaseTemperature

RL =480

4 X IC @ 250C

DUT10ΩΩ

32µµF600V480V

Figure 8. Pulsed Collector Current Test Circuit

40HFL60

DUT10ΩΩ

32µµF600V480V

Figure 9. Clamped Inductive Load Test Circuit

10µµH

AN-983 (v.Int)

The reverse recovery is a significant contributor to turn-on losses. To discriminate between the losses that are intrinsicto the IGBT and those due to the diode reverse recovery, the test circuit shown in Figure 16 has been used togenerate the data sheet values.

Emitter-to-Collector Breakdown Voltage (BV ECS). This ratingcharacterizes the reverse breakdown of the unterminated collector-basejunction of the PNP. The relevance of this specification and its associatedreverse avalanche energy can be better understood with reference to Figure11. When an IGBT turns off and current is transferred to the diode across thecomplementary device, the turn-off di/dt in the stray inductance that is inseries with the diode generates a reverse voltage spike across the IGBT (i.e.,the collector voltage goes negative with respect to the emitter). This reversevoltage is typically less than 10V, though higher voltages can result from veryhigh di/dt or poor layout. Since this reverse voltage can cause avalanche inthe junction, International Rectifier IGBTs have an energy rating, given inthe Absolute Maximum Ratings table, that is more useful to the designer thana traditional diode characterization. This rating is typically an order ofmagnitude more than what would be required by the user.

Collector-to-Emitter Saturation Voltage (V CE(on)). Being the key ratingto calculate conduction losses, this value is supported by three figures thatprovide a detailed characterization in temperature, current and gate voltage(Figures 14, 15, and 16 for the IRGBC20U). These replace the older formatshown in Figure 12 and 13.

Gate Threshold Voltage (V GE(th)). This is the range of voltage on the gateat which collector current starts to flow. The variation in gate threshold withtemperature is also specified (∆VGE(th) / ∆Τj). Typically the coefficient is -11mV/°C, leading to a reduction of about 1.4V in the threshold voltage at hightemperature.

Forward Transconductance (g FE). This parameter is measured bysuperimposing a small variation on a gate bias that takes the IGBT to its100°C rated current in "linear" mode. As mentioned in Section 7,transconductance increases significantly with current so that the "currentthroughput" of an IGBT is not limited by gain, as a bipolar, but by thermalconsiderations.

IC

VCE

VCE : 100V/div.IC : 5A./div., 0.1 µµs/div

Figure 10a . Turn-on with a clampedinductive load and a fast recovery diode.Test circuit as in Figure 9.

VCE

IC

VCE : 100V/div.IC : 5A./div., 0.1 µµs/div

Figure 10b . Turn-on with an ideal diode(zener clamp). Test circuit as in Figure 16.

D1T1

LS

LS

D2

T2

Figure 11. When T2 goes off, loadcurrent flows into the diode inparallel with T1. The reverse turn-off di/dt of T2 developes a voltageacross the stray inductance inseries with D1 which reversebiases T1. IR's IGBTs have aspec i f i ed reve rse b lock ingcapab i l i t y (BV C E S ) a n d a navalanche rating (ERV)

AN-983 (v.Int)

Zero-Gate-Voltage Collector Current (I CES). This parameter guarantees the upper limit of the leakage distribution at therated voltage and two temperatures. It complements the BVCES rating seen above.

8.5. Switching Characteristics

GateChargeParameters(Q g, Qge, Qgc). Gate charge values of an IGBT are useful to size the gate drive circuit and estimatinggate drive losses. Unfortunately they cannot be used to predict switching times, as for a power MOSFET, because of theminority carrier nature of this device. The test method and the characteristics described in the application note INT-944. Figure17 gives the typical value of the total gate charge as a function of the voltage applied to the gate. The shape of the curve isexplained in detail in INT-944.

Switching Times (t d, tr, tf). The switching times for a simple IGBT are defined with reference to the Switching Loss TestCircuit of Figure 18. Those for co-paks are defined with reference to the Clamped Inductive Load of Figure 19.

For a simple device, they are defined as follows:

• Turn-on delay time: 10% of gate voltage to 10% of collector current• Rise time: 10 to 90% of collector current• Turn-off delay time: 90% of gate voltage to 90% of collector current• Fall time: 90 to 10% of collector current.

For a copak, they are defined as follows:

• Turn-on delay time: 10% of gate voltage to 10% of collector current• Rise time: 10 to 90% of collector current• Turn-off delay time: 90% of gate voltage to 10% of collector voltage• Fall time: 90 to 10% of collector current.

Switching times provide a useful guideline to establish the appropriate deadtime between the turn-off and subsequent turn-on ofcomplementary devices in a half bridge configuration and the minimum and maximum pulse widths. They provide a veryunreliable indication of switching losses. Because of the current tail mentioned in Section 8.2, a significant part of the turn-offenergy may be dissipated as the current is below 10%. The voltage fall time, on the other hand, is not characterized in any way.Thus, two significant contributors to losses are not properly accounted for by the switching times. Switching losses are fullycharacterized as such in the data sheet, as explained in the next paragraph.

5.0V

20µµs PULSE WIDTHTj = 250C

VGE50V15V10V7.0V5.0V

TOP

BOTTOM

0 2 4 6 8 1010-1

100

101

Vce, COLLECTOR-TO-EMITTER VOLTAGE (VOLTS)

Ic, C

OLL

EC

TO

R-T

O-E

MIT

TE

R C

UR

RE

NT

(A

MP

S)

Figure 13. Typical Output Characteristics, Tc = 1500C

0

5.0V

20µµs pulse widthTj = 250C

VGE50V15V10V7.0V5.0V

TOP

BOTTOM

2 4 6 8 1010-2

10-1

100

101

Vce, COLLECTOR-TO-EMITTER VOLTAGE (VOLTS)

Ic, C

OLL

EC

TO

R-T

O-E

MIT

TE

R C

UR

RE

NT

(A

MP

S)

Figure 12. Typical Output Characteristics. Tc = 250C

AN-983 (v.Int)

It should be remembered that IGBTs, like power MOSFETs,do not have a storage time. The turn-off delay is due to theMiller effect, as explained in Section I.A of INT-990.

Switching Energy (E on, Eoff , Ets). IGBTs fromInternational Rectifier have a guaranteed switching energyproviding a full characterization in terms of temperature,collector current and gate resistance (Figures 20, 21 and 22for the IRGBC20U). This allows the designer to calculatethe switching losses, without worrying about the actualcurrent and voltage waveshapes, the tail and the quasi-saturation.

Any test circuit for measuring switching losses has to satisfytwo fundamental requirements:

1. It must simulate the switching conditions as they areencountered in a practical application, i.e., a clampedinductive load with continuous current flow.

2. It must reflect the losses that are attributable to the

IGBT, and must be independent from those due to othercircuit components, like the reverse recovery of thefreewheeling diode.

The test circuit that meets these requirements for a simple IGBT is shown in Figure 18. Its operation is as follows:The driver IGBT builds the test current in the inductor. When it is turned off, current flows in the zener. At this point theswitching time and switching energy test begins, by turning on and off the device under test (DUT). The DUT will see the testcurrent that was flowing into the inductor and the voltage across the zener, without any reverse recovery component from afreewheeling diode. This test can exercise the IGBT to its full voltage and current without any spurious effect due to diodereverse recovery.

The test method, on the other hand, must account for all losses that occur because of the switching operation, including the quasi-saturation at turn-on and the tail at turn-off. To fulfill this requirement, the energy figures reported in the data sheet are definedas follows:

Tj = 1500C

Tj = 250C

1

VGE = 15V20µµs PULSE WIDTH

10

10

100

VCE, Collector-to-emitter Voltage (V)

I C, C

olle

ctor

-to-

emitt

er C

urre

nt (

A)

Figure 14 . Figure 15.

Tj = 1500C

Tj = 1500C

VCC = 100V5ms PULSE WIDTH

5 10 15 200.1

1

10

100

VGE, Gate-to-emitter Voltage (V)

IC, G

ate-

to-e

mitt

er C

urre

nt (

A)

Vge = 15V80ms pulse width

Ic = 13A

Ic = 6.5A

Ic = 3.3A

-60 -40 -20 0 20 40 60 80 100 120 140 1601.0

2.0

3.0

4.0

Tc, CASE TEMPERATURE ( 0C)

Vce

, CO

LLE

CT

OR

-TO

-EM

ITT

ER

VO

LTA

GE

(V

OLT

S)

Figure 16. Collector-to-Emitter Saturation Voltagevs. Case Temperature

AN-983 (v.Int)

Eon: From 5% of test current to 5% of test voltage. We feel that5% is a reasonable compromise between the resolution of theinstrumentation and the need to account for the quasi-saturationthat could occur in some devices.

Eoff : This energy is measured over a period of time that startswith 5% of test voltage and goes on for 5 µsec. While thecurrent tail of most IGBTs would be finished well before thattime, it was felt that the contribution of the leakage losses to thetotal energy is minimal.

Ets: This is the sum of the turn-on and turn-off losses. As shownin Figure 22, switching energy for International Rectifier IGBTsis closely proportional to current. This is not necessarily true forIGBTs from other manufacturers. The test circuit for a co-pack,on the other hand, should include the losses due to the diode,assuming a clamped inductive load with an identical device in acomplementary position (Figure 19). The definitions are asfollows:

Eon: From 10% of test current to 5% of test voltage.

Eoff : This energy is measured over aperiod of time that starts with 10% oftest voltage and goes on for 5 µsec.

Internal Emitter Inductance (L E)This is the package inductancebetween the bonding pad on the dieand the electrical connection at thelead. This inductance slows down theturn-on of the IGBT by an amount thatis proportional to the di/dt of thecollector current, just like the Millereffect slows it down by an amount thatis proportional to the collector dv/dt.With a di/dt of 1000 A/µsec, thevoltage developed across thisinductance is in excess of 7V.

Device Capacitances (C iee, Coee,Cree). The test circuit and a briefexplanation of the test method can befound in Figure 20. The outputcapacitance has the typical voltagedependence of a P-N junction. Thereverse transfer (Miller) capacitance isalso strongly dependent on voltage(inversely proportional), but in a morecomplex way than the outputcapacitance. The input capacitance,which is the sum of the gate-to-emitterand of the Miller capacitance, showsthe same voltage dependence of theMiller capacitance but in a veryattenuated form since the gate-to-emitter capacitance is much larger andvoltage independent.

Vce = 480VIc = 6.5A

0 4 8 12 16 200

4

8

12

16

20

Qg, TOTAL GATE CHARGE (nC)

Vge

, GA

TE

-TO

-EM

ITT

ER

VO

LTA

GE

(V

OLT

S)

Figure 17. Typical Gate Charge vs. Gate - to -Emitter Voltage

1

2

3

90%

10%

90%VC

10%5%

td(off)

tr tf

Eoff

Eon

IC

t = 5 µµs

Ets = (Eon + Eoff )

Figure 18b.

LC

* DRIVER SAME TYPE AS DUTVC = 80% OF BVCES

1

23

DUTDRIVER *

Figure 18a

Figure 18. Switching Loss Test Circuit and Waveforms

AN-983 (v.Int)

D.U.T.

Same typedevice asD.U.T.

430µµF80%

of Vce

Figure 19a.t1 t2

5% Ic

90% Ic

Ic

Vce

tftd (off)

Ic

10%Vce

+ Vge90% Vge

∫∫Eoff =t1+5µµsVce Ic dtt1

Figure 19b.

t1 t2

∫∫Eon =t2Vce Ic dtt1

5%Vce

trtd (on)

10%Ic

90% IcIpk Ic

DUT VOLTAGEAND CURRENT

+Vg10% +Vg

Vce

GATE VOLTAGE DUT

Vcc

Figure 19c.t3 t4

DIODE REVERSERECOVERYENERGY

DIODEREVERSEWAVEFORMS

∫∫Erec=t4Vd Id dtt3

Vcc10% Irr

∫∫Qrr=trrId dttx

trr

10% Vcctx

Ic

Vpk

Figure 19d.Vg GATE SIGNAL DEVICE UNDER TEST

CURRENTD.U.T.

VOLTAGE IND.U.T.

CURRENT IND1

Figure 19e.

AN-983 (v.Int)

The Transfer Characteristic (Figure 15 for the IRGBC20U). This curve deviates from the traditional definition of transfercharacteristic in one detail: the drain is not connected to the gate but to a fixed (100V) supply. When gate and drain are tiedtogether, the curve is the boundary separating operation in full enhancement from operation in linear mode (sometimes referredto as "sat mode"). Figure 15 provides an indication of current when operated in short circuit. In the normal range of operationthis curve shows a slight negative dependence on temperature and is largely independent from applied voltage.

The Short-Circuit Withstand Time (for short-circuit rated IGBTs) defines the guaranteed minimum time the IGBT can be inshort circuit in the specified conditions. Notice that the gate resistor cannot be any lower than specified and the overvoltage atturn-off has to be maintained to the indicated value by an appropriate clamp.

If a diode is copackaged with the IGBT, its characteristics are included in this table, together with their associated graphs. Theparameters included in the table are defined in application note AN-989.

9: The IGBT Families from IR

Table II may be useful in placing different powertransistors in the proper perspective. In general, the IGBToffers clear advantages in high voltage (>300V), highcurrent (1-3 A/mm2 of active area), and medium speed (to5-50 kHz). International Rectifier’s technology ischaracterized by very low voltage drop per unit of currentdensity. This allows higher levels of minority lifetimekilling and, consequently, much lower switching losses.

To maximize the value to the user of its technologicalbreakthrough, International Rectifier has introduced threedifferent families of devices with different crossoverfrequency: Standard, Fast and UltraFast. IR's Standard IGBTs have been optimized for voltage dropand conduction losses and have the lowest voltage drop perunit of current density that is presently available in themarket.

Vce = 480VVge = 15VTc = 250CIc = 6.5A

0.350

0.345

0.340

0.335

0.330

0.325

0.32020 25 30 35 40 45 50 55

Rg, GATE RESISTANCE (OHMS)

TO

TA

L S

WIT

CH

ING

EN

ER

GY

LO

SS

ES

(m

J)

Figure 20. Typical Switching Losses vs. GateResistance

Vge = 15VVcc = 480VRg = 50ΩΩ

Ic = 13A

Ic = 6.5A

Ic = 3.3A

-60 -40 -20 0 20 40 60 80 100 120 140 16010-1

100

Tc, CASE TEMPERATURE ( 0C)

TO

TA

L S

WIT

CH

ING

EN

ER

GY

LO

SS

ES

(m

J)

Figure 21. Typical Switching Losses vs. CaseTemperature

Tc = 1500CRg = 250ΩΩVcc = 480VVge = 15V

3 6 9 12 150.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

Ic, COLLECTOR-TO-EMITTER CURRENT (AMPS)

TO

TA

L S

WIT

CH

ING

EN

ER

GY

LO

SS

ES

(m

J)

Figure 22. Typical Switching Losses vs. CollectorCurrent

AN-983 (v.Int)

IR's UltraFast IGBTs have been optimized for switching losses and have the lowest switching losses per unit of current densitypresently available in the market.

As it is apparent from Figure 24, these devices have switching speeds that are comparable to those of power MOSFETs inpractical applications. They can operate comfortably at 50 kHz in PWM and well over 100 kHz in resonant or ZVS/ZCS circuits.

The IGBT is biased with 25V between collector and emitter. Two of its terminals are ac shorted with a large valuecapacitor. Capacitance is measured between these two terminals and the third.

IR's Fast devices offer a combination of low switching and low conduction losses that closely matches the switchingcharacteristics of many popular bipolar transistors. Table III shows the key features of the three families. The Fast and UltrafastIGBTs are also available in short-circuit rated versions for those applications, like motor drives, that require it. The short circuitcapability comes at the expenses of a slight increase in conduction losses.

10M

C2LOW

HIGH

CAPACITANCEMETER

DUT

1µµFBIAS

VOLTAGE

620K

620K

Ciee = Ccg + Cge =

=1

1Cmeasured

- 1C2

Figure 23a.

Figure 23c.

Figure 23b.

C2

LOW

HIGH

CAPACITANCEMETER

DUT

BIASVOLTAGE

620K

620K

Coee = Ccg + Cce =

=1

1Cmeasured

- 1C2

10:1LOW

HIGH

CAPACITANCEMETER

DUT

BIASVOLTAGE

620K

620K

Cree = Ccg

=

1µµf

10M

Figure 23. Capacitance test circuits

AN-983 (v.Int)

POWER MOSFETs IGBTs Bipolars DarlingtonsType of Drive Voltage Voltage Current CurrentDrive Power Minimal Minimal Large Medium

Drive Complexity Simple Simple HighLarge positive and

negative currents arerequired

Medium

Current DensityFor Give Voltage

Drop

High at low voltages

Low at high voltages

Very HighSmall trade-off with

switching speed

MediumSevere trade-off with

switching speed

Low

Switching Losses Very Low Low to Mediumdepending on trade-offwith conduction losses

Medium to Highdepending on trade-offwith conduction losses

High

Table II: Comparative Table of Power Transistor Characteristics

References:

1. U.S. Patents No. 4,376,286 and 4,642,666

Characteristic Standard Fast UltrafastVCE

Switching Energy

Conduction Losses(50% dc)

1.3V

0.54 mJ/A mm2

0.625W

1.5V

0.16 mJ/A mm2

0.75W

1.9V

0.055mJ/A mm2

0.95W

Table III. International Rectifier IGBT Families1A/mm2, 1000C, Typical Values

Figure 24. IRGPC50U switching 50A at 480V, 1250C. Test circuit is as shown in Figure 16.

VCE

IC

ENERGY

VCE : 100V/div.

IC : 10a/div.E : 0.5µµJ/div., 0.1ms/div.

Figure 24a.

VCE

IC

ENERGYVCE : 100V/div.IC : 10A/div.E : 0.5 mJ/div., 0.1 µµs/div

Figure 24b.

IRG4BC30UDINSULATED GATE BIPOLAR TRANSISTOR WITHULTRAFAST SOFT RECOVERY DIODEFeaturesFeaturesFeaturesFeaturesFeatures

E

G

n-cha nn e l

C

VCES = 600V

VCE(on) typ. = 1.95V

@VGE = 15V, IC = 12A

Parameter Min. Typ. Max. UnitsRθJC Junction-to-Case - IGBT ------ ------ 1.2RθJC Junction-to-Case - Diode ------ ------ 2.5 °C/WRθCS Case-to-Sink, flat, greased surface ------ 0.50 ------RθJA Junction-to-Ambient, typical socket mount ----- ----- 80Wt Weight ------ 2 (0.07) ------ g (oz)

Thermal Resistance

UltraFast CoPack IGBT

4/17/00

Absolute Maximum Ratings Parameter Max. Units

VCES Collector-to-Emitter Voltage 600 VIC @ TC = 25°C Continuous Collector Current 23IC @ TC = 100°C Continuous Collector Current 12ICM Pulsed Collector Current 92 AILM Clamped Inductive Load Current 92IF @ TC = 100°C Diode Continuous Forward Current 12IFM Diode Maximum Forward Current 92VGE Gate-to-Emitter Voltage ± 20 VPD @ TC = 25°C Maximum Power Dissipation 100PD @ TC = 100°C Maximum Power Dissipation 42TJ Operating Junction and -55 to +150TSTG Storage Temperature Range °C

Soldering Temperature, for 10 sec. 300 (0.063 in. (1.6mm) from case)Mounting Torque, 6-32 or M3 Screw. 10 lbf•in (1.1 N•m)

• UltraFast: Optimized for high operating frequencies 8-40 kHz in hard switching, >200 kHz in resonant mode• Generation 4 IGBT design provides tighter parameter distribution and higher efficiency than Generation 3• IGBT co-packaged with HEXFREDTM ultrafast, ultra-soft-recovery anti-parallel diodes for use in bridge configurations• Industry standard TO-220AB packageBenefits• Generation -4 IGBT's offer highest efficiencies available• IGBTs optimized for specific application conditions• HEXFRED diodes optimized for performance with IGBTs . Minimized recovery characteristics require less/no snubbing• Designed to be a "drop-in" replacement for equivalent industry-standard Generation 3 IR IGBTs

PD 91453B

W

TO-220AB

www.irf.com 1

IRG4BC30UD

2 www.irf.com

Parameter Min. Typ. Max. Units ConditionsQg Total Gate Charge (turn-on) ---- 50 75 IC = 12AQge Gate - Emitter Charge (turn-on) ---- 8.1 12 nC VCC = 400V See Fig. 8Qgc Gate - Collector Charge (turn-on) ---- 18 27 VGE = 15Vtd(on) Turn-On Delay Time ---- 40 ---- TJ = 25°Ctr Rise Time ---- 21 ---- ns IC = 12A, VCC = 480Vtd(off) Turn-Off Delay Time ---- 91 140 VGE = 15V, RG = 23Ωtf Fall Time ---- 80 130 Energy losses include "tail" andEon Turn-On Switching Loss ---- 0.38 ---- diode reverse recovery.Eoff Turn-Off Switching Loss ---- 0.16 ---- mJ See Fig. 9, 10, 11, 18Ets Total Switching Loss ---- 0.54 0.9td(on) Turn-On Delay Time ---- 40 ---- TJ = 150°C, See Fig. 9, 10, 11, 18tr Rise Time ---- 22 ---- ns IC = 12A, VCC = 480Vtd(off) Turn-Off Delay Time ---- 120 ---- VGE = 15V, RG = 23Ωtf Fall Time ---- 180 ---- Energy losses include "tail" andEts Total Switching Loss ---- 0.89 ---- mJ diode reverse recovery.LE Internal Emitter Inductance ---- 7.5 ---- nH Measured 5mm from packageCies Input Capacitance ---- 1100 ---- VGE = 0VCoes Output Capacitance ---- 73 ---- pF VCC = 30V See Fig. 7Cres Reverse Transfer Capacitance ---- 14 ---- ƒ = 1.0MHztrr Diode Reverse Recovery Time ---- 42 60 ns TJ = 25°C See Fig.

---- 80 120 TJ = 125°C 14 IF = 12AIrr Diode Peak Reverse Recovery Current ---- 3.5 6.0 A TJ = 25°C See Fig.

---- 5.6 10 TJ = 125°C 15 VR = 200VQrr Diode Reverse Recovery Charge ---- 80 180 nC TJ = 25°C See Fig.

---- 220 600 TJ = 125°C 16 di/dt 200A/µsdi(rec)M/dt Diode Peak Rate of Fall of Recovery ---- 180 ---- A/µs TJ = 25°C See Fig.

During tb ---- 120 ---- TJ = 125°C 17

Parameter Min. Typ. Max. Units ConditionsV(BR)CES Collector-to-Emitter Breakdown Voltage 600 ---- ---- V VGE = 0V, IC = 250µA∆V(BR)CES/∆TJ Temperature Coeff. of Breakdown Voltage ---- 0.63 ---- V/°C VGE = 0V, IC = 1.0mAVCE(on) Collector-to-Emitter Saturation Voltage ---- 1.95 2.1 IC = 12A VGE = 15V

---- 2.52 ---- V IC = 23A See Fig. 2, 5---- 2.09 ---- IC = 12A, TJ = 150°C

VGE(th) Gate Threshold Voltage 3.0 ---- 6.0 VCE = VGE, IC = 250µA∆VGE(th)/∆TJ Temperature Coeff. of Threshold Voltage ---- -11 ---- mV/°C VCE = VGE, IC = 250µAgfe Forward Transconductance 3.1 8.6 ---- S VCE = 100V, IC = 12AICES Zero Gate Voltage Collector Current ---- ---- 250 µA VGE = 0V, VCE = 600V

---- ---- 2500 VGE = 0V, VCE = 600V, TJ = 150°CVFM Diode Forward Voltage Drop ---- 1.4 1.7 V IC = 12A See Fig. 13

---- 1.3 1.6 IC = 12A, TJ = 150°CIGES Gate-to-Emitter Leakage Current ---- ---- ±100 nA VGE = ±20V

Switching Characteristics @ TJ = 25°C (unless otherwise specified)

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

IRG4BC30UD

www.irf.com 3

Fig. 1 - Typical Load Current vs. Frequency (Load Current = IRMS of fundamental)

Fig. 2 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics

0.1

1

1 0

1 0 0

0.1 1 1 0

C E

CI ,

Col

lect

or-t

o-E

mitt

er C

urre

nt (

A)

V , C o lle cto r-to -E m itte r V o lta g e (V )

T = 1 50 °C

T = 2 5 °C

J

J

V = 1 5 V2 0 µ s P U LS E W ID T H

G E

A 0.1

1

1 0

1 0 0

5 6 7 8 9 1 0 1 1 1 2

CI ,

Col

lect

or-t

o-E

mitt

er C

urre

nt (

A)

G E

T = 2 5 °C

T = 1 50 °C

J

J

V , G a te -to -E m itte r Vo lta g e (V )

A

V = 10 V5 µ s P U L S E W ID T H

C C

Load

Cur

rent

( A

)

0

4

8

1 2

1 6

0.1 1 1 0 1 0 0

f, Frequency (kHz)

A

6 0 % o f ra te d vo l ta g e

I

D uty c yc le : 5 0%T = 12 5° CT = 90 °CG a te d rive a s s pe c ifiedTurn -o n losse s in clud eeffects of re verse re co very

s in kJ

Powe r D is sipatio n = 21 W

IRG4BC30UD

4 www.irf.com

Fig. 5 - Typical Collector-to-Emitter Voltagevs. Junction Temperature

Fig. 4 - Maximum Collector Current vs.Case Temperature

Fig. 6 - Maximum IGBT Effective Transient Thermal Impedance, Junction-to-Case

0

5

1 0

1 5

2 0

2 5

2 5 5 0 7 5 1 0 0 1 2 5 1 5 0

Ma

xim

um

DC

Co

llec

tor

Cu

rre

nt

(A

T , C a se Te m p e ra tu re (°C )C

V = 1 5 V G E

A

0.01

0 .1

1

10

0 .00001 0 .0001 0 .001 0 .01 0 .1 1 10

t , Rectangular Pulse Duration (sec)1

thJC

D = 0.50

0 .010 .02

0 .05

0.10

0.20

S IN GLE PU LS E(TH E R MAL RE S PON SE )

The

rmal

Res

pons

e (Z

)

P

t 2

1t

DM

N otes : 1 . D u ty fac tor D = t / t

2 . P eak T = P x Z + T

1 2

J DM th JC C

1 .5

2 .0

2 .5

3 .0

-60 -40 -20 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0C

EV

, Col

lect

or-t

o-E

mitt

er V

olta

ge (

V) V = 1 5 V

8 0 µ s P U LS E W ID T HG E

A

T , Ju n c tio n T e m p e ra tu re (°C )J

I = 2 4 A

I = 1 2 A

I = 6 .0 AC

C

C

IRG4BC30UD

www.irf.com 5

Fig. 7 - Typical Capacitance vs.Collector-to-Emitter Voltage

Fig. 8 - Typical Gate Charge vs.Gate-to-Emitter Voltage

Fig. 9 - Typical Switching Losses vs. GateResistance

Fig. 10 - Typical Switching Losses vs.Junction Temperature

0

4 0 0

8 0 0

1 2 0 0

1 6 0 0

2 0 0 0

1 1 0 1 0 0

C E

C,

Ca

pa

cita

nce

(p

F)

V , C o lle c to r- to -E m itte r V o lta g e (V )

A

V = 0V , f = 1M H zC = C + C , C S H O R TE DC = CC = C + C

G Eies ge gc ceres gcoes ce gc

C ie s

C re s

C o e s

0

4

8

1 2

1 6

2 0

0 1 0 2 0 3 0 4 0 5 0G

EV

, G

ate

-to

-Em

itte

r V

olta

ge

(V)

gQ , T o ta l G a te C h a rg e (n C )

A

V = 4 0 0 V I = 1 2 A

C E

C

Tot

al S

witc

hig

Loss

es (

mJ)

0 .1

1

1 0

-60 -40 -20 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0

A

T , Junction Temperature (°C)J

R = 23Ω V = 15V V = 480V

I = 24A

I = 12A

I = 6.0A

G

G E

C C

C

C

C

Tot

al S

witc

hig

Loss

es (

mJ)

0 . 50

0 .52

0 .54

0 .56

0 .58

0 .60

0 1 0 2 0 3 0 4 0 5 0 6 0

G

A

R , Gate Resistance ( Ω)

V = 480V V = 15V T = 25°C I = 12A

C C

G E

J

C

IRG4BC30UD

6 www.irf.com

Fig. 11 - Typical Switching Losses vs.Collector-to-Emitter Current

Fig. 12 - Turn-Off SOA

Fig. 13 - Maximum Forward Voltage Drop vs. Instantaneous Forward Current

1

10

100

0.4 0.8 1.2 1.6 2.0 2.4

FM

FIn

sta

nta

ne

ou

s F

orw

ard

Cu

rre

nt

- I

(

A)

Fo rward Voltage Drop - V (V)

T = 150°C

T = 125°C

T = 25°C

J

J

J

0 .1

1

10

100

1000

1 10 100 1000C

C E

G E

V , Collecto r-to-Em itter Voltage (V )

I ,

Col

lect

or-to

-Em

itter

Cur

rent

(A)

S A FE O P E R A TING A R E A

V = 20V T = 125 °C

G EJ

0.0

0.4

0 .8

1 .2

1 .6

2 .0

0 1 0 2 0 3 0

CI , Collector-to-Emitter Current (A )

A

R = 23 Ω T = 150°C V = 480V V = 15V

G

J

C C

G E

Tot

al S

witc

hig

Loss

es (

mJ)

IRG4BC30UD

www.irf.com 7

Fig. 14 - Typical Reverse Recovery vs. dif/dt Fig. 15 - Typical Recovery Current vs. dif/dt

Fig. 16 - Typical Stored Charge vs. dif/dt Fig. 17 - Typical di(rec)M/dt vs. dif/dt

0

200

400

600

100 1000fd i /d t - (A/µs)

RR

Q

-

(nC

)

I = 6.0A

I = 12A

I = 24A

V = 200 VT = 1 25 °CT = 2 5 °C

R

J

J

F

F

F

10

100

1000

10000

100 1000fd i /d t - (A /µ s)

di(

rec)

M/d

t -

(A

/µs)

I = 12A

I = 24A

I = 6.0A

F

F

F

V = 200 VT = 1 25 °CT = 2 5 °C

R

J

J

0

40

80

120

160

100 1000fd i /d t - (A/µs)

t

-

(ns)

rr

I = 24A

I = 12A

I = 6 .0AF

F

F

V = 200 VT = 1 25 °CT = 2 5 °C

R

J

J

1

10

100

100 1000fd i /dt - (A/µs)

I

-

(A)

IRR

M

I = 6 .0A

I = 12A

I = 24AF

F

F

V = 200 VT = 1 25 °CT = 2 5 °C

R

J

J

IRG4BC30UD

8 www.irf.com

t1

Ic

V ce

t1 t2

90% Ic10% V ce

td (o ff) tf

Ic

5% Ic

t1+ 5µ SV ce ic d t

90% V ge

+ V ge

∫E of f =

Fig. 18b - Test Waveforms for Circuit of Fig. 18a, DefiningEoff, td(off), tf

∫ V ce ie d tt2

t1

5% V ce

IcIpkV cc

10% Ic

V ce

t1 t2

D U T V O LT A G EA N D C U R R E N T

G A T E V O LT A G E D .U .T .

+ V g10% +V g

90% Ic

trtd (on)

D IO D E R E V E R S ER E C O V E R Y E N E R G Y

tx

E on =

∫E rec =t4

t3V d id d t

t4t3

D IO D E R E C O V E R YW A V E FO R M S

Ic

V pk

10% V cc

Irr

10% Irr

V cc

trr ∫Q rr =trr

tx id d t

Same typedevice asD .U.T.

D .U .T.

430µF80%of Vce

Fig. 18a - Test Circuit for Measurement ofILM, Eon, Eoff(diode), trr, Qrr, Irr, td(on), tr, td(off), tf

Fig. 18c - Test Waveforms for Circuit of Fig. 18a,Defining Eon, td(on), tr

Fig. 18d - Test Waveforms for Circuit of Fig. 18a,Defining Erec, trr, Qrr, Irr

IRG4BC30UD

www.irf.com 9

V g G A T E S IG N A LD E V IC E U N D E R T E S T

C U R R E N T D .U .T .

V O LT A G E IN D .U .T .

C U R R E N T IN D 1

t0 t1 t2

D.U.T.

V *c

50V

L

1000V

6000µ F 100 V

RL=480V

4 X IC @25°C0 - 480V

INSTITUTO DE ELETRÔNICA DE POTÊNCIA

DEPARTAMENTO DE ENGENHARIA ELÉTRICACENTRO TECNOLÓGICOUNIVERSIDADE FEDERAL DE SANTA CATARINA

MCT

G

A

K

Acadêmico Cássio Guimarães LopesProf. Arnaldo José Perin

Florianópolis, março de 1996

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 2

ÍNDICE

Assunto Página

Introdução 3

Princípio de Funcionamento 4

Características 5

Parâmetros 6

Operação 8

Forma de Onda da Tensão de Gatilho 8

Amplitude Negativa 9

Transição Negativa 9

Amplitude Positiva 9

Transição Positiva 9

Área de Operação Segura de Bloqueio 10

Circuitos de Comando 10

Coeficiente de Temperatura da Tensão 12

Comparação: IGBT versus MCT 13

Queda de Tensão em Condução 13

Comutação 13

Tensão de Operação Segura de Bloqueio 14

Onde Usar o MCT? 14

Referências Bibliográficas 15

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 3

INTRODUÇÃO

A eletrônica de potência invariavelmente soluciona problemas relacionados à

utilização de energia elétrica. Progressos nesta área traduzem-se, freqüentemente, na dependência

do aperfeiçoamento ou do desenvolvimento de novos interruptores à base de dispositivos

semicondutores.

Um novo dispositivo semicondutor de potência, o “MOS Controlled Thyristor”, ou

simplesmente MCT - já disponível comercialmente - emerge como uma alternativa ímpar para a

implementação e projeto das estruturas envolvidas em eletrônica de potência. Possui seu próprio

conjunto de características, embora carregue consigo semelhanças com interruptores mais antigos,

como SCRs ou GTOs.

Objetivando a familiarização com o componente, descreve-se de maneira genérica,

porém concisa, o seu funcionamento e suas principais características, não havendo compromisso

com o aprofundamento do assunto, o que torna-se possível consultando as referências bibliográficas

apresentadas.

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 4

PRINCÍPIO DE FUNCIONAMENTO

A figura 1 mostra o circuito equivalente do MCT tipo P, o P-MCT, baseado no

modelo de tiristor a dois transistores. Nota-se também a presença de dois FETs, responsáveis pelo

disparo e bloqueio via gatilho - o arranjo permite o comando do MCT através da tensão gate-anodo,

VGA .

No P-MCT, o mosfet canal P realiza o disparo. Aplicando-se tensão VGA negativa, o

“PFET” é acionado, polarizando a base do transistor inferior (NPN), o que coloca o MCT em

condução.

ANODO

PFET-DISPARO

NFET-BLOQUEIO

GATILHO

CATODO

Fig. 1 - Circuito Equivalente

O bloqueio é proporcionado, via gatilho, pela aplicação de tensão VGA positiva. O

mosfet canal N entra em condução, desviando a corrente de emissor do transistor PNP

bloqueando-o. Isto provoca o corte da corrente de polarização da base do transistor NPN,

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 5

interrompendo a corrente de catodo do MCT e efetuando o seu bloqueio. O MCT também é

bloqueado por corrente reversa, como ocorre com tiristores comuns.

CARACTERÍSTICAS

Pela sua constituição, o MCT combina a capacidade de corrente dos tiristores com a

alta impedância de entrada das portas MOS, permitindo o controle de disparo/bloqueio por tensão.

A figura 2 apresenta sua simbologia.

GATILHO

RETORNOGATILHO

ANODO

CATODO

G

A

K

Fig. 2 - Simbologia

A primeira geração de P-MCT, 600 V, é constituída de cerca de 11.000 grupos de

células em paralelo. Cada grupo constitue-se de 9 células de 0.4 cm2 , uma das quais destina-se ao

disparo, sendo rodeada pelas 8 restantes responsáveis pelo bloqueio.

O MCT apresenta diversas vantagens quando comparado com os interruptores

tradicionais utilizados em eletrônica de potência:

• A alta impedância do gatilho MOS exige uma quantidade mínima de energia para a comutação,

simplificando os circuitos de comando;

• Possui baixa queda de tensão em condução;

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 6

• Grande capacidade de di/dt e dv/dt;

• Baixa capacitância de entrada, tipicamente 10 nF, não apresentando “corrente Miller” na

comutação;

• Excelente capacidade de corrente: para quedas de tensão similares, pode apresentar densidades

de corrente centenas de vezes maior que seu contemporâneo IGBT (figura 3);

• Tiristores, GTOs e MCTs podem apresentar queda de tensão em condução reduzida, porém este

último possuirá dimensões menores (economia de silício);

• Para uma mesma quantidade de silício, o MCT apresenta queda de tensão bem inferior quando

comparado a outros interruptores como GTOs ou tiristores comuns;

• São fabricados sobre uma ampla faixa de valores, de 100V a 8KV, podendo alcançar os 10KV. O

bloqueio pode ser simétrico ou assimétrico (suporta apenas tensões positivas ou também

negativas).

PARÂMETROS

O MCT assemelha-se em certos aspectos aos tiristores. Muitos parâmetros

encontrados em seus manuais são idênticos aos presentes nos manuais dos FETs de potência.

Entretanto, alguns parâmetros são diferentes dos convencionais:

• Tensão de Bloqueio de Pico (MCT Bloqueado), VDRM - máxima tensão permissível entre catodo e

anodo;

• Tensão de Pico Reversa, VRRM - o MCT não é projetado como um componente de bloqueio de

tensão reversa mas, como o IGBT, possui capacidade de bloqueio suficiente para permitir o uso

de um diodo em antiparalelo;

• Corrente de Catodo de Pico Não Repetitiva, ITSM - é a máxima corrente permissível através do

componente sob o formato de um pulso. A temperatura da junção limita sua amplitude e largura;

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 7

• Corrente Controlável de Pico, ITC - representa o máximo valor de corrente de catodo bloqueável

através do sinal de gatilho. Bloquear correntes que ultrapassem este valor pode significar a

destruição do componente;

0 0.5 1.0 1.5 2 2.51

10

100

1000

1 104

N-MCT

P-MCT

N-IGBT

DARLINGTON

N-MOSFET

DENSIDADEDE CORRENTE

(A/cm2)

TEMPERATURA: 25 Co

QUEDA DE TENSÃO (VOLTS)

Fig. 3 - Comparação entre alguns Interruptores de Potência

• Tensão Gate-Anodo (pico), VGA - o componente permite sobretensões (“overshoot”) durante as

transições de bloqueio e disparo;

• Máxima Potência Dissipada, PT - é função da máxima resistência térmica junção-

encapsulamento (0,6oC/W) e da máxima diferença de temperatura junção-encapsulamento

(+125oC).

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 8

OPERAÇÃO

Certos cuidados devem ser tomados para a operação com sucesso.

Segundo testes realizados pelo fabricante (HARRIS) , o MCT operou bloqueando

80A a 300oC, suportando dV/dt’s de 10KV/µs a 250oC. Com a junção a uma temperatura de 235oC,

ele suportou cerca de 100 horas ao teste de vida de bloqueio. Recomenda-se para tanto, manter-se

continuamente a polarização do gatilho.

Forma de Onda da Tensão de Gatilho

O desempenho do MCT está ligado diretamente à forma de onda da tensão de

gatilho. O seu funcionamento é mapeado na figura 4, que serve como base para a definição de

valores de tensão para o circuito de comando.

0

5

10

15

20

25

-5

-10

-15

-20

-25

0 1 2 0 1 2

REGIÃOSEGURAMCT EM MCT EM

REGIÃOSEGURA

REGIÃOSEGURA

MCT BLOQUEADO

TRANSIÇÃO

TRANSIÇÃO

POSITIVA

NEGATIVA

(BLOQUEIO)

(DISPARO)

(BLOQUEIO) (DISPARO)

TEMPO

VGA(VOLTS)

usEM

CONDUÇÃO CONDUÇÃO

Fig. 4 - Limites da Forma de Onda da Tensão de Gatilho

Durante a ocorrência dos pulsos de comando (amplitude constante) deve-se

caracterizar a forma de onda pelas regiões seguras. Nos períodos de transição, o sinal de gatilho

deve enquadrar-se nas áreas sombreadas.

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 9

Amplitude Negativa

A tensão limite de -7V na região segura (figura 4) coloca o componente em

condução com certo atraso. A tensão de -20V, ainda na região segura, limita o funcionamento

normal do MCT sem danificá-lo por tensão excessiva.

Transição Negativa

Distintamente no MCT, o gatilho (valor de tensão) não pode ser usado no controle do

tempo de disparo, o que pode ser conseguido variando-se a inclinação da transição negativa da

tensão.

Quando o período da transição é reduzido, a corrente de deslocamento provocará o

disparo com a tensão de gatilho ainda positiva.

Amplitude Positiva

Com a aplicação de tensão gate-anodo positiva, o MCT é bloqueado e assim

permanece.

O bloqueio da corrente é conseguido com uma tensão da ordem de 18V com uma

duração mínima de 1,5 µs. Limita-se em 20V a tensão na região segura a fim de se evitar a

destruição por excesso da mesma. Permite-se que a tensão alcance os 25V nas transições.

Transição Positiva

Para maximizar a capacidade de bloqueio, deve-se acionar o gatilho rapidamente.

Caso o crescimento da tensão ocorra de maneira lenta, a corrente será redistribuida nas células

internas alcançando valores que impossibilitarão o bloqueio. Isto estabelece 200 ns como limite de

tempo para a transição positiva.

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 10

Área de Operação Segura de Bloqueio

Similarmente a outros interruptores a semicondutor tipo P, o P-MCT apresenta

limitações na área de operação segura de bloqueio (SOA). Basicamente três fatores são incisivos na

capacidade de comutação:

∗ Tempo de subida da Tensão de Gatilho: para valores superiores ao recomendado

anteriormente, a área de operação segura será delimitada abaixo da curva mostrada na figura 5.

∗ Tensão de Gatilho durante o Bloqueio: a tensão de gatilho deve alcançar e manter os

valores anteriormente indicados sob pena da redução da região superior plana da curva.

∗ Tensão VKA de Pico: na região de alta tensão da curva a capacidade de comutação é

influenciada por este valor. Aconselha-se a aplicação de sobretensão (25 V) durante a comutação

para o auxílio do bloqueio.

Circuitos de Comando

Os circuitos de comando destinados ao MCT devem apresentar as seguintes

características:

∗ Tensão de Comando de Gatilho: superior a ± 20V;

∗ Tempo de Subida/Descida: < 200ns;

∗ Corrente de pico: superior a 2A;

∗ Interface de sinal: isolação ótica ou magnética;

∗ Isolação de Potência: o circuito de comando deve ser fisicamente conectado ao anodo do

MCT. Requer-se isolamento da tensão de barramento e capacidade de suportar dv/dt resultante das

comutações.

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 11

0102030405060708090100110120130140150160170

0 -50 -150 -250 -350 -450 -550

Tj=+150 C, Vg=18V,L=200uoIk (A)

VKA (VFig. 5 - Curva de Capacidade de Bloqueio Típica

A tensão de gatilho pico a pico requerida limita as escolhas de CI’s que possam

comandar diretamente o MCT.

Os circuitos de comando são tipicamente energizados por um transformador e um

retificador para prover a isolação CC.

O sinal de comando geralmente será acoplado por fibra ótica ou por meio de um

optoacoplador.

Uma opção de circuito de comando implementada e testada por Franklin Miguel [4],

é apresentada na figura 6.

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 12

D1R2

D2

Q1

G ARG

Vin

D3

D4

Q2

1N4148

1N4148

1N4148

1N4148

BD139

BD140

W 1

W 470

C13.3 nF

C21 nF

R3W 330

CB10 uF

RBW 330

CA22 uF

RAW 470

Q32N3819

R1W 540

+20V +20V+20V

Fig. 6 - Sugestão para circuito de Comando

Coeficiente de Temperatura da Tensão

Um importante aspecto da queda de tensão em condução é o valor de corrente para o

qual o coeficiente de temperatura é zero. Abaixo deste valor o coeficiente é negativo, ou seja, a

tensão decresce com a temperatura. Acima do mesmo a queda de tensão em condução aumenta

conjuntamente com a corrente, denotando um coeficiente de temperatura positivo.

Do ponto de vista do paralelismo, é vantajoso fixar-se na região de coeficiente

positivo. Dependendo da configuração do circuito, pode-se operar acima da capacidade de

comutação de pico de um único componente. Para a operação acima da corrente de coeficiente de

temperatura zero, o circuito deve ser ressonante ou a mesma deve ser conduzida a um nível de

comutação segura.

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 13

COMPARAÇÃO: MCT VERSUS IGBT

Em muitas aplicações, os requisitos de cada circuito específico pode influenciar

bastante na comparação.

Ambos possuem o gatilho isolado, são interruptores controlados por campo, com

valores da temperatura da junção em torno de 150oC. Sendo uma “mescla” bipolar/MOS, as duas

estruturas são aplicáveis em circuitos de comutação de potência onde requer-se 600V ou mais,

usados também em freqüências de comutação mais altas do que geralmente é praticado com

transistores Darlington de potência.

Em circuitos de alta potência, a remoção de calor tem impacto significativo no

tamanho e na natureza do encapsulamento. Portanto, perdas de comutação e em condução perfazem

o primeiro confronto dos citados a seguir:

Queda de Tensão em Condução

A mais importante característica do MCT é a queda de tensão em condução, com

valores situados de 1/3 a 1/2 dos valores do IGBT, aumentando modestamente mesmo em grandes

picos de corrente, diferindo do seu concorrente.

Comutação

O disparo no MCT é iniciado pelo gatilho e completado regenerativamente como um

SCR. Apresenta rapidez, grande capacidade de di/dt e de picos de corrente, com baixas perdas em

condução.

No IGBT o disparo é, com freqüência, intencionalmente lento para controlar a

recuperação reversa do diodo de circulação, porém com sacrifício das perdas em condução.Os

melhores IGBTs fabricados atualmente podem superar o “então” P-MCT na velocidade de bloqueio

apresentando menores perdas por ciclo de comutação (grosseiramente por um fator 2).

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 14

A decisão final a ser tomada para a escolha do componente depende da proporção

entre as perdas no chaveamento e em conducão, ou seja, dependerá do circuito em questão.

Tensão de Operação Segura de Bloqueio (SOA)

A área de operação segura de bloqueio descreve o lugar geométrico das combinações

permissíveis de tensão e corrente através do interruptor que não provoque a sua operação indevida.

Para o P-MCT, a corrente nominal de bloqueio é sustentável de 50% a 60% do valor

da tensão de ruptura, contra os 80% do IGBT, que apresenta uma melhor área de operação segura.

ONDE USAR O MCT?

Em qualquer circuito dominado por perdas de condução, a primeira geração de P-

MCT pode reduzir pela metade as perdas e a área ativa de silício: um componente menor e mais

eficiente.

Na substituição a GTOs e transistores bipolaress, ele oferece a considerável

vantagem do gatilho MOS.

Também em circuitos de comutação dissipativa, em freqüências de muitos KHz e

abaixo, o P-MCT pode ser uma boa escolha, apesar da provável necessidade de um circuito

limitador de tensão (geralmente um simples capacitor: “snubber”) para mantê-lo na área de

operação segura.

O seu uso pode tornar-se desinteressante em circuitos onde as perdas de comutação

são equivalentes às perdas de condução. Na substituição de um IGBT com perdas de condução de

50W e de comutação de 30W por exemplo, o lucro seria pequeno: a primeira geração de MCTs tipo

P, apresentaria perdas por condução < 25W, mas suas perdas de comutação seriam

aproximadamente 60W.

MCT - MOS CONTROLLED THYRISTOR

INEP - INSTITUTO DE ELETRÔNICA DE POTÊNCIA 15

Em circuitos de comutação dissipativa ou PWM, as baixas perdas de comutação do

IGBT sobrepujam as baixas perdas de condução do MCT, particularmente em freqüências acima de

10 Khz.

Em circuitos PWM, a maior tensão na área de operação segura de bloqueio do IGBT

de 600V, cerca de 480V, podem torná-lo a solução preferida para tensões contínuas entre 300V e

400V. Com MCTs tipo P o uso de capacitores limitadores ou componentes com valores mais

elevados torna-se necessário para a operação nesta mesma faixa.

Circuitos de descarga de pulso geralmente favorecem o MCT, devido à velocidade de

disparo e grande capacidade de picos de corrente sob baixa queda de tensão.

Apesar de suas características, o MCT ainda não preenche todos as lacunas em

eletrônica de potência. Em freqüências de comutação acima de 50Khz na comutação dissipativa e

acima de 100Khz na comutação suave, os MOSFETs de potência ainda afirmam-se como a única

solução prática no momento (1995).

REFERÊNCIAS BIBLIOGRÁFICAS

[1] V. Temple, “Power Device Evolution and the MOS-Controlled Thyristor”, PCIM, Nov,1987pp 23-29;

[2] V.A.K. Temple, S. D. Arthur et al., “Megawatt MOS Controlled Thyristor for High VoltagePower Circuits”, PESC 92 Proceedings, pp 1018-1025 (Toledo, Spain, June 29 - July 3, 1992)

[3] Manual do Fabricante - “Harris Semiconductor”, 1994.

[4] Franklin Miguel, “MCT”, Relatório de Estágio, PET-EEL, 1995.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.

Copyright © Harris Corporation 19992-18

SemiconductorMCTV75P60E1,MCTA75P60E1

75A, 600VP-Type MOS Controlled Thyristor (MCT)

PackageJEDEC STYLE TO-247 5-LEAD

JEDEC MO-093AA (5-LEAD TO-218)

Symbol

ANODE ANODECATHODE

GATE RETURNGATE

ANODE ANODECATHODE

GATE RETURNGATE

G A

K

Features• 75A, -600V

• VTM = -1.3V(Maximum) at I = 75A and +150 oC

• 2000A Surge Current Capability

• 2000A/µs di/dt Capability

• MOS Insulated Gate Control

• 120A Gate Turn-Off Capability at +150 oC

DescriptionThe MCT is an MOS Controlled Thyristor designed for switchingcurrents on and off by negative and positive pulsed control of aninsulated MOS gate. It is designed for use in motor controls,inverters, line switches and other power switching applications.

The MCT is especially suited for resonant (zero voltage orzero current switching) applications. The SCR like forwarddrop greatly reduces conduction power loss.

MCTs allow the control of high power circuits with very smallamounts of input energy. They feature the high peak currentcapability common to SCR type thyristors, and operate atjunction temperatures up to +150oC with active switching.

PART NUMBER INFORMATION

PART NUMBER PACKAGE BRAND

MCTV75P60E1 TO-247 MV75P60E1

MCTA75P60E1 MO-093AA MA75P60E1

NOTE: When ordering, use the entire part number.

April 1999

Absolute Maximum Ratings TC = +25oC, Unless Otherwise Specified

MCTV75P60E1MCTA75P60E1 UNITS

Peak Off-State Voltage (See Figure 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDRM -600 V

Peak Reverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VRRM +5 V

Continuous Cathode Current (See Figure 2)TC = +25oC (Package Limited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TC = +90oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK25

IK90

8575

AA

Non-Repetitive Peak Cathode Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IKSM 2000 A

Peak Controllable Current (See Figure 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IKC 120 A

Gate-Anode Voltage (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA ±20 V

Gate-Anode Voltage (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGAM ±25 V

Rate of Change of Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dv/dt See Figure 11

Rate of Change of Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . di/dt 2000 A/µs

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT 208 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.67 W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to +150 oC

Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(0.063" (1.6mm) from case for 10s)

TL 260 oC

NOTE:

1. Maximum Pulse Width of 250µs (Half Sine) Assume TJ (Initial) = +90oC and TJ (Final) = TJ (Max) = +150oC

File Number 3374.6

PART WITHDRAWN

PROCESS OBSOLETE - NO NEW DESIGNS

2-19

Specifications MCTV75P60E1, MCTA75P60E1

Electrical Specifications TC = +25oC Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Peak Off-StateBlocking Current

IDRM VKA = -600V,

VGA = +18V

TC = +150oC - - 3 mA

TC = +25oC - - 100 µA

Peak ReverseBlocking Current

IRRM VKA = +5V

VGA = +18V

TC = +150oC - - 4 mA

TC = +25oC - - 100 µA

On-State Voltage VTM IK = IK90,

VGA = -10V

TC = +150oC - - 1.3 V

TC = +25oC - - 1.4 V

Gate-AnodeLeakage Current

IGAS VGA = ±20V - - 200 nA

Input Capacitance CISS VKA = -20V, TJ = +25oCVGA = +18V

- 10 - nF

Current Turn-OnDelay Time

tD(ON)I L = 200µH, IK = IK90RG = 1Ω, VGA = +18V, -7VTJ = +125oCVKA = -300V

- 300 - ns

Current Rise Time tRI - 200 - ns

Current Turn-OffDelay Time

tD(OFF)I - 700 - ns

Current Fall Time tFI - 1.15 1.4 µs

Turn-Off Energy EOFF - 10 - mJ

Thermal Resistance RθJC - .5 .6 oC/W

Typical Performance Curves

FIGURE 1. CATHODE CURRENT vs SATURATION VOLTAGE(TYPICAL)

FIGURE 2. MAXIMUM CONTINUOUS CATHODE CURRENT

300

100

10

1

I K, C

ATH

OD

E C

UR

RE

NT

(A

)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VTM, CATHODE VOLTAGE (V)

PULSE TESTPULSE DURATION - 250µsDUTY CYCLE < 2%

TJ = +150oC

TJ = +25oC

TJ = -40oC

120

110

100

90

80

70

60

50

40

30

20

10

025 35 45 55 65 75 85 95 105 115 125 135 145 155

TC, CASE TEMPERATURE (oC)

I K, D

C C

ATH

OD

E C

UR

RE

NT

(A

)

PACKAGE LIMIT

2-20

MCTV75P60E1, MCTA75P60E1

FIGURE 3. TURN-ON DELAY vs CATHODE CURRENT(TYPICAL)

FIGURE 4. TURN-OFF DELAY vs CATHODE CURRENT(TYPICAL)

FIGURE 5. TURN-ON RISE TIME vs CATHODE CURRENT(TYPICAL)

FIGURE 6. TURN-OFF FALL TIME vs CATHODE CURRENT(TYPICAL)

FIGURE 7. TURN-ON ENERGY LOSS vs CATHODE CURRENT(TYPICAL)

FIGURE 8. TURN-OFF ENERGY LOSS vs CATHODE CURRENT(TYPICAL)

Typical Performance Curves (Continued)

500

400

300

200

100

010 20 30 40 50 60 70 80 90 100 110 120

TD

(ON

)I ,

TU

RN

-ON

DE

LAY

(ns

)

IK, CATHODE CURRENT (A)

TJ = +150oC, RG = 1Ω, L = 200µH

VKA = -300V

VKA = -200V

10

VKA = -300V

VKA = -200V

20 30 40 50 60 70 80 90 110100 1200.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

TD

(OF

F)I ,

TU

RN

-OF

F D

ELA

Y (

µs)

IK, CATHODE CURRENT (A)

TJ = +150oC, RG = 1Ω, L = 200µH

TJ = +150oC, RG = 1Ω, L = 200µH

10 20 30 40 50 60 70 80 90 100 110 120

500

400

300

200

100

0

tR

I, R

ISE

TIM

E (

ns)

IK , CATHODE CURRENT (A)

VKA = -300V

VKA = -200V

TJ = +150oC, RG = 1Ω, L = 200µH

10 20 30 40 50 60 70 80 90 100 110 120

2.0

1.6

1.2

0.8

0.4

0.0

tF

I , F

ALL

TIM

E (

µs)

IK , CATHODE CURRENT (A)

VKA = -300V

VKA = -200V

1.8

1.4

1.0

0.6

0.2

TJ = +150oC, RG = 1Ω, L = 200µH

10 20 30 40 50 60 70 80 90 100 110 120

5.0

1.0

0.1

IK, CATHODE CURRENT (A)

VKA = -300V

VKA = -200V

EO

N, T

UR

N-O

N S

WIT

CH

ING

LO

SS

(m

J)

TJ = +150oC, RG = 1Ω, L = 200µH

10 20 30 40 50 60 70 80 90 100 110 120

20.0

10.0

1.0 EO

FF,

TU

RN

-OF

F S

WIT

CH

ING

LO

SS

(mJ)

IK , CATHODE CURRENT (A)

VKA = -300V

VKA = -200V

2-21

MCTV75P60E1, MCTA75P60E1

FIGURE 9. OPERATING FREQUENCY vs CATHODE CURRENT(TYPICAL)

FIGURE 10. TURN-OFF CAPABILITY vs ANODE-CATHODEVOLTAGE

FIGURE 11. BLOCKING VOLTAGE vs dv/dt FIGURE 12. SPIKE VOLTAGE vs di/dt (TYPICAL)

Typical Performance Curves (Continued)

EON = tD(ON) I = 0

EON ≠ 0, tD(ON) I ≠ 0

VKA = -200V

VKA = -300V

fMAX1 = 0.05(tD(ON) I + tD(OFF) I)fMAX2 = (PD - PC) / ESWITCH

PD: ALLOWABLE DISSIPATIONPC: CONDUCTION DISSIPATION(PC DUTY FACTOR = 50%)RθJC = 0.5oC/W

10 100 200 IK , CATHODE CURRENT (A)

100

10

1

fM

AX

, M

AX

OP

ER

ATIN

G F

RE

QU

EN

CY

(kH

z)

TJ = +150oC, VGA = 18V, L = 200µH1501401301201101009080706050403020100

0 -50 -150 -250 -350 -450 -550 VKA , PEAK TURN OFF VOLTAGE (V)

TURN-OFFSAFE OPERATING AREA

I K ,

PE

AK

CAT

HO

DE

CU

RR

EN

T (

A)

TJ = +150oC, VGA = 18V

-500

-525

-550

-575

-600

-625

-650

-675

-700

0.1 1.0 10.0 100.0 1000.0 10000.0dv/dt (V/ µs)

-425

-450

-475

-725

VD

RM

, BR

EA

KD

OW

N V

OLT

AG

E (

V)

1 6 11 16 21 26 31 36 41 46

-200

-100

-1

SP

IKE

VO

LTA

GE

(V

)

di/dt (A/ µs)

-10CS = 2µF, TJ = +150oC

CS = 2µF, TJ = +25oC

CS = 0.1µF, TJ = +150oC

CS = 0.1µF, TJ = +25oC

CS = 1µF, TJ = +150oC

CS = 1µF, TJ = +25oC

Operating Frequency InformationOperating frequency information for a typical device(Figure 9) is presented as a guide for estimating device per-formance for a specific application. Other typical frequencyvs cathode current (IAK) plots are possible using the informa-tion shown for a typical unit in Figures 3 to 8. The operatingfrequency plot (Figure 9) of a typical device shows fMAX1 orfMAX2 whichever is smaller at each point. The information isbased on measurements of a typical device and is boundedby the maximum rated junction temperature.

fMAX1 is defined by fMAX1 = 0.05 / (tD(ON)I + tD(OFF)I). tD(ON)I +tD(OFF)I deadtime (the denominator) has been arbitrarily held to10% of the on-state time for a 50% duty factor. Other definitionsare possible. tD(ON)I is defined as the 10% point of the leadingedge of the input pulse and the point where the cathode currentrises to 10% of its maximum value. tD(OFF)I is defined as the90% point of the trailing edge of the input pulse and the pointwhere the cathode current falls to 90% of its maximum value.Device delay can establish an additional frequency limiting condi-

tion for an application other than TJMAX. tD(OFF)I is importantwhen controlling output ripple under a lightly loaded condition.

fMAX2 is defined by fMAX2 = (PD - PC) / (EON + EOFF). Theallowable dissipation (PD) is defined by PD = (TJMAX - TC) /RΘJC. The sum of device switching and conduction lossesmust not exceed PD. A 50% duty factor was used (Figure 10)and the conduction losses (PC) are approximated by PC =(VAK • IAK) / (duty factor/100). EON is defined as the sum ofthe instantaneous power loss starting at the leading edge ofthe input pulse and ending at the point where the anode-cathode voltage equals saturation voltage (VAK = VTM). EOFFis defined as the sum of the instantaneous power loss start-ing at the trailing edge of the input pulse and ending at thepoint where the cathode current equals zero (IK = 0).

The switching power loss (Figure 10) is defined as fMAX2 • (EON+ EOFF). Because Turn-on switching losses can be greatly influ-enced by external circuit conditions and components, fMAXcurves are plotted both including and neglecting turn-on losses.

2-22

MCTV75P60E1, MCTA75P60E1

Test Circuits

FIGURE 13. SWITCHING TEST CIRCUIT FIGURE 14. VSPIKE TEST CIRCUIT

FIGURE 15. SWITCHING TEST WAVEFORMS FIGURE 16. VSPIKE TEST WAVEFORMS

+

-

200µH RURG8060

VKIK

DUT

9V

20V

VA

IK

VG

500Ω

CS

10kΩ 4.7kΩ

DUT

+

-

+ -

-

+

I K

VG

tF ItD(OFF) I tR I

tD(ON) I

10%

90%

10%

90%

-VKA

MAXIMUM RISE AND FALL TIME OF V G IS 200ns

IK

VAK

VG

VTM

VSPIKE

di/dt

Handling Precautions for MCT'sMOS Controlled Thyristors are susceptible to gate-insula-tion damage by the electrostatic discharge of energy throughthe devices. When handling these devices, care should beexercised to assure that the static charge built in the han-dler's body capacitance is not discharged through thedevice. MCT's can be handled safely if the following basicprecautions are taken:

1. Prior to assembly into a circuit, all leads should be keptshorted together either by the use of metal shortingsprings or by the insertion into conductive material suchas *“ECCOSORB LD26” or equivalent.

2. When devices are removed by hand from their carriers,the hand being used should be grounded by any suitablemeans - for example, with a metallic wristband.

3. Tips of soldering irons should be grounded.

4. Devices should never be inserted into or removed from cir-cuits with power on.

5. Gate Voltage Rating - Never exceed the gate-voltagerating of VGA. Exceeding the rated VGA can result inpermanent damage to the oxide layer in the gate region.

6. Gate Termination - The gates of these devices are essen-tially capacitors. Circuits that leave the gate open-circuitedor floating should be avoided. These conditions can resultin turn-on of the device due to voltage buildup on the inputcapacitor due to leakage currents or pickup.

7. Gate Protection - These devices do not have an internalmonolithic zener diode from gate to emitter. If gate protec-tion is required an external zener is recommended.

† Trademark Emerson and Cumming, Inc.